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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-02 22:19:50 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-02 22:22:31 -0800 |
| commit | 86925506c6ed8516dceca45a53fbac4d845f096c (patch) | |
| tree | 344d74acebfd8ec5a8e313b64f319c4d448508e6 /src/machine.tex | |
| parent | fc41db64f3cf618534adf02422db1ea4deb3ce4f (diff) | |
| download | riscv-isa-manual-86925506c6ed8516dceca45a53fbac4d845f096c.zip riscv-isa-manual-86925506c6ed8516dceca45a53fbac4d845f096c.tar.gz riscv-isa-manual-86925506c6ed8516dceca45a53fbac4d845f096c.tar.bz2 | |
Remove PLIC chapter from privileged spec
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index ccf2ace..a6a83a8 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1334,8 +1334,7 @@ on the platform specification. The MEIP field in {\tt mip} is a read-only bit that indicates a machine-mode external interrupt is pending. MEIP is set and cleared by a platform-specific -interrupt controller, such as the standard platform-level interrupt controller -specified in Chapter~\ref{plic}. The MEIE field in {\tt mie} enables machine +interrupt controller. The MEIE field in {\tt mie} enables machine external interrupts when set. The SEIP field in {\tt mip} contains a single read-write bit. SEIP |