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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-08-18 01:11:56 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-18 01:11:56 -0700 |
| commit | 7446cb34b2877aefd19847181090c8b030395b5c (patch) | |
| tree | 6d813f07eb52e5c404497db169d1fcb8711b1f23 /src/machine.tex | |
| parent | 3bf08168b2f84dc6e16a107fdf90be59586caf5d (diff) | |
| download | riscv-isa-manual-7446cb34b2877aefd19847181090c8b030395b5c.zip riscv-isa-manual-7446cb34b2877aefd19847181090c8b030395b5c.tar.gz riscv-isa-manual-7446cb34b2877aefd19847181090c8b030395b5c.tar.bz2 | |
Tweak table of synchronous exception priorities (#716)
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/machine.tex b/src/machine.tex index ab4a21e..6e52218 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2063,7 +2063,7 @@ a policy on whether these need to be distinguished, and if so, whether a given opcode should be treated as illegal or privileged. \end{commentary} -If an instruction raises multiple synchronous exceptions, the +If an instruction may raise multiple synchronous exceptions, the decreasing priority order of Table~\ref{exception-priority} indicates which exception is taken and reported in {\tt mcause}. The priority of any custom synchronous exceptions is implementation-defined. @@ -2073,7 +2073,7 @@ The priority of any custom synchronous exceptions is implementation-defined. \begin{tabular}{|l|r|l|} \hline - Priority & Exc. Code & Description \\ + Priority & Exc.\@ Code & Description \\ \hline {\em Highest} & 3 & Instruction address breakpoint \\ \hline @@ -2081,7 +2081,7 @@ The priority of any custom synchronous exceptions is implementation-defined. & 12, 1 & \quad First encountered page fault or access fault \\ \hline - & & With physical instruction address: \\ + & & With physical address for instruction: \\ & 1 & \quad Instruction access fault \\ \hline & 2 & Illegal instruction \\ @@ -2095,7 +2095,7 @@ The priority of any custom synchronous exceptions is implementation-defined. \hline & & During address translation for an explicit memory access: \\ - & 5, 7, 13, 15 & \quad First encountered page fault or + & 13, 15, 5, 7 & \quad First encountered page fault or access fault \\ \hline & & With physical address for an explicit @@ -2112,7 +2112,8 @@ The priority of any custom synchronous exceptions is implementation-defined. \label{exception-priority} \end{table*} -When address translation is performed, the address translation +When a virtual address is translated into +a physical address, the address translation algorithm determines what specific exception may be raised. Load/store/AMO address-misaligned exceptions may have |