diff options
| author | Andrew Waterman <andrew@sifive.com> | 2021-09-02 17:47:02 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-02 17:47:02 -0700 |
| commit | 73bca53b4cf21f6ec39262e4472d4fa7a7e48551 (patch) | |
| tree | 6682262d79b689a42bd3a20f57675b8c16c307ce /src/machine.tex | |
| parent | 9f7f7083b0e6a546430f34da339f07a919f64164 (diff) | |
| download | riscv-isa-manual-73bca53b4cf21f6ec39262e4472d4fa7a7e48551.zip riscv-isa-manual-73bca53b4cf21f6ec39262e4472d4fa7a7e48551.tar.gz riscv-isa-manual-73bca53b4cf21f6ec39262e4472d4fa7a7e48551.tar.bz2 | |
Describe purpose of FIOM mechanism
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index f4ef940..3f921f5 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2381,6 +2381,12 @@ for modes less privileged than M when FIOM=1.% \label{tab:menvcfg-FIOM} \end{table} +\begin{commentary} +Bit FIOM is needed in {\tt menvcfg} so M-mode can emulate the +hypervisor extension of Chapter~\ref{hypervisor}, which has an +equivalent FIOM bit in the hypervisor CSR {\tt henvcfg}. +\end{commentary} + The definition of the STCD field will be furnished by the forthcoming Sstc extension. Its allocation within {\tt menvcfg} may change prior to the ratification |