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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2021-12-06 00:22:34 -0800 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2021-12-06 00:22:34 -0800 |
| commit | 5cc0aa8d84464a4eee71713c5566d64cf3c4bdda (patch) | |
| tree | bed6ccaf4f045c375ff3cfcce98db6cd4d347cbc /src/machine.tex | |
| parent | b67ae1c988af3736549baaec413583d036b9e682 (diff) | |
| download | riscv-isa-manual-5cc0aa8d84464a4eee71713c5566d64cf3c4bdda.zip riscv-isa-manual-5cc0aa8d84464a4eee71713c5566d64cf3c4bdda.tar.gz riscv-isa-manual-5cc0aa8d84464a4eee71713c5566d64cf3c4bdda.tar.bz2 | |
Remove unfriendly terminology.
No normative change.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/src/machine.tex b/src/machine.tex index adb789c..d2c7ed3 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2958,7 +2958,7 @@ as instruction, load, or store access-fault exceptions, distinct from virtual-memory page-fault exceptions. Precise PMA traps might not always be possible, for example, when probing a legacy bus architecture that uses access failures as part of the discovery mechanism. In this -case, error responses from slave devices will be reported as imprecise +case, error responses from peripheral devices will be reported as imprecise bus-error interrupts. PMAs must also be readable by software to correctly access certain @@ -3150,7 +3150,7 @@ model. Incoherent main memory regions have an implementation-defined memory model. Accesses by one hart to an I/O region are observable not only by other harts -and bus mastering devices but also by targeted slave I/O devices, and I/O +and bus mastering devices but also by the targeted I/O devices, and I/O regions may be accessed with either {\em relaxed} or {\em strong} ordering. Accesses to an I/O region with relaxed ordering are generally observed by other harts and bus mastering devices in a manner similar to the ordering of @@ -3221,16 +3221,6 @@ incoherent during the transition between cacheability settings. This transitory state should not be visible to lower privilege levels. \begin{commentary} -We categorize RISC-V caches into three types: {\em master-private}, -{\em shared}, and {\em slave-private}. Master-private caches are -attached to a single master agent, i.e., one that issues read/write -requests to the memory system. Shared caches are located between -masters and slaves and may be hierarchically organized. Slave-private -caches do not impact coherence, as they are local to a single slave -and do not affect other PMAs at a master, so are not considered -further here. We use {\em private cache} to mean a master-private -cache in the following section, unless explicitly stated otherwise. - Coherence is straightforward to provide for a shared memory region that is not cached by any agent. The PMA for such a region would simply indicate it should not be cached in a private or shared cache. |