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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-02 17:42:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-02 17:42:16 -0700 |
| commit | 5bce9789a9183f553ca444d820e9152bde442c54 (patch) | |
| tree | dd71952ec71d542dd8edcb7d4330495333551a32 /src/machine.tex | |
| parent | 3879ff36fd78d81665b2309fc33617364fec05c2 (diff) | |
| download | riscv-isa-manual-5bce9789a9183f553ca444d820e9152bde442c54.zip riscv-isa-manual-5bce9789a9183f553ca444d820e9152bde442c54.tar.gz riscv-isa-manual-5bce9789a9183f553ca444d820e9152bde442c54.tar.bz2 | |
Pedantically clarify behavior of writing lo/hi parts of counters
Writing the low part does not disturb the high part and vice versa.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index 2ed1235..bad69d6 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1679,10 +1679,11 @@ A future revision of this specification will define a mechanism to generate an interrupt when a hardware performance monitor counter overflows. \end{commentary} -On RV32 only, reads of the {\tt mcycle}, {\tt minstret}, and {\tt -mhpmcounter{\em n}} CSRs return the low 32 bits, while reads of the {\tt -mcycleh}, {\tt minstreth}, and {\tt mhpmcounter{\em n}h} CSRs return bits -63--32 of the corresponding counter. +When MXLEN=32, reads of the {\tt mcycle}, {\tt minstret}, and {\tt +mhpmcounter{\em n}} CSRs return bits 31--0 of the corresponding counter, and +writes change only bits 31--0; reads of the {\tt mcycleh}, {\tt minstreth}, +and {\tt mhpmcounter{\em n}h} CSRs return bits 63--32 of the corresponding +counter, and writes change only bits 63--32. \begin{figure}[h!] {\footnotesize |