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| author | Andrew Waterman <andrew@sifive.com> | 2021-08-29 22:32:20 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-29 22:32:20 -0700 |
| commit | 46a2569962d2d65a4362427163278820acb0b453 (patch) | |
| tree | b82d95fcdfa96dcf129936c6fee2c807735446f9 /src/machine.tex | |
| parent | d7b5caa893ecd40d295f5ae9831a055dcd1d0b70 (diff) | |
| download | riscv-isa-manual-46a2569962d2d65a4362427163278820acb0b453.zip riscv-isa-manual-46a2569962d2d65a4362427163278820acb0b453.tar.gz riscv-isa-manual-46a2569962d2d65a4362427163278820acb0b453.tar.bz2 | |
FIOM affects aq/rl, too
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 4ecc7ec..ae4b5f6 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2351,6 +2351,12 @@ to order main memory accesses. Table~\ref{tab:menvcfg-FIOM} details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO for modes less privileged than M when FIOM=1. + +Similarly, for modes less privileged than M when FIOM=1, +if an atomic instruction that accesses a region ordered as device I/O +has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered +as though it accesses both device I/O and memory. + If U-mode is not supported, FIOM is hardwired to zero. \begin{table}[h!] |