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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-09-24 00:30:50 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-09-24 00:30:50 -0700 |
| commit | 3666bb19913ddbc893f9cfc74da8af6f6ae046be (patch) | |
| tree | 3abf72a7095db9c2aa31aa0378626f0bc2d425d9 /src/machine.tex | |
| parent | 4c6ee856fcd8576d582a14b55fdab4e72483a804 (diff) | |
| download | riscv-isa-manual-3666bb19913ddbc893f9cfc74da8af6f6ae046be.zip riscv-isa-manual-3666bb19913ddbc893f9cfc74da8af6f6ae046be.tar.gz riscv-isa-manual-3666bb19913ddbc893f9cfc74da8af6f6ae046be.tar.bz2 | |
Improving lanuage.
Closed #215
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index ba1e1aa..0deda94 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1733,10 +1733,10 @@ and virtual addresses. It need not be capable of holding all possible invalid addresses. Implementations may convert some invalid address patterns into other invalid addresses prior to writing them to {\tt mepc}. -When a trap is taken into M-mode, {\tt mepc} is written with the virtual -address of the instruction that encountered the exception or was interrupted. -Otherwise, {\tt mepc} is never written by the implementation, though it may be -explicitly written by software. +When a trap is taken into M-mode, {\tt mepc} is written with the +virtual address of the instruction that was interrupted or that +encountered the exception. Otherwise, {\tt mepc} is never written by +the implementation, though it may be explicitly written by software. \begin{figure}[h!] {\footnotesize |