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| author | Andrew Waterman <andrew@sifive.com> | 2021-11-30 16:46:22 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-11-30 16:46:22 -0800 |
| commit | 1c6a1402c928b7d1108b8cb49bb8c7e173887d7b (patch) | |
| tree | 677e950e3c31d0d4963e766407bb2a3c48291546 /src/machine.tex | |
| parent | c89daecdb305b8980156e27c332b261065a1d0ee (diff) | |
| download | riscv-isa-manual-1c6a1402c928b7d1108b8cb49bb8c7e173887d7b.zip riscv-isa-manual-1c6a1402c928b7d1108b8cb49bb8c7e173887d7b.tar.gz riscv-isa-manual-1c6a1402c928b7d1108b8cb49bb8c7e173887d7b.tar.bz2 | |
Permit speculative execution of HLV/HSV; reset hgatp.MODE, satp.MODE
Final architecture-review item for hypervisor extension v1.0.
The draft specification inadvertently made it very difficult to
speculatively execute HLV/HSV instructions, but we would prefer to allow
them to speculatively execute like regular loads and stores.
However, doing so can cause functional problems if hgatp/vsatp contain
garbage out of reset (random page table walks, possibly to I/O regions,
might occur due to speculative execution within M-mode). So, reset those
CSRs' MODE fields.
However, speculative execution of HLV/HSV opens an unfortunate side
channel: HS-mode speculation could cause VS-stage PTE.A bits to be set,
which is architecturally visible to VS-mode. Explicitly prohibit this
from happening. (We note this doesn't close related microarchitectural
side channels.)
Finally, make it clear that hgatp/vsatp are "active" for page-table
walking purposes in more situations, since speculative execution of
HLV/HSV can trigger page-table walks in M-/HS-modes (or U mode when
hstatus.HU=1).
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index fb3b270..8062600 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2851,6 +2851,8 @@ reset vector. The {\tt mcause} register is set to a value indicating the cause of the reset. Writable PMP registers' A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers' A and L fields. +If the hypervisor extension is implemented, the {\tt hgatp}.MODE and +{\tt vsatp}.MODE fields are reset to 0. No \warl\ field contains an illegal value. All other hart state is \unspecified. |