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| author | Andrew Waterman <andrew@sifive.com> | 2021-08-11 14:24:21 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-11 14:24:21 -0700 |
| commit | 1317718847de08fc74ca25e1c01b54cdee0d86d1 (patch) | |
| tree | b816c4fe2954b2d0e9978a6612e646c4153bdf88 /src/machine.tex | |
| parent | 50694a2c0d5393690a9e0c8d309cf064f6c8c0e4 (diff) | |
| download | riscv-isa-manual-1317718847de08fc74ca25e1c01b54cdee0d86d1.zip riscv-isa-manual-1317718847de08fc74ca25e1c01b54cdee0d86d1.tar.gz riscv-isa-manual-1317718847de08fc74ca25e1c01b54cdee0d86d1.tar.bz2 | |
Generalize interrupt trap condition evaluation conditions (#705)
This approach is more extensible, and now implicitly includes
writes to sstatus.SIE / mstatus.MIE, as it should.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index da03202..c3d51ea 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1387,7 +1387,9 @@ privilege than M-mode; These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes pending in {\tt mip}, and must also be evaluated immediately following the execution of an {\em x}\/RET -instruction or an explicit write to {\tt mip} or {\tt mie}. +instruction or an explicit write to a CSR on which these interrupt trap +conditions expressly depend (including {\tt mip}, {\tt mie}, {\tt mstatus}, +and {\tt mideleg}). Interrupts to M-mode take priority over any interrupts to lower privilege modes. |