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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-09-15 15:24:46 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-15 15:24:46 -0700 |
| commit | 073d6371a4989c58330ba6c8c6ba3c508381e08e (patch) | |
| tree | a0c990d481559cdc32756f3c142076b5176a2d78 /src/machine.tex | |
| parent | ca16943e9330a1a937438e72e26c1189cfe20c4a (diff) | |
| download | riscv-isa-manual-073d6371a4989c58330ba6c8c6ba3c508381e08e.zip riscv-isa-manual-073d6371a4989c58330ba6c8c6ba3c508381e08e.tar.gz riscv-isa-manual-073d6371a4989c58330ba6c8c6ba3c508381e08e.tar.bz2 | |
mip.MSIP and mie.MSIE may be hardwired zeros (#738)
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index ca8f7a1..5d0d60e 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1528,6 +1528,10 @@ to memory-mapped control registers, which are used by remote harts to provide machine-level interprocessor interrupts. A hart can write its own MSIP bit using the same memory-mapped control register. +If a system has only one hart, or if a platform standard supports the +delivery of machine-level interprocessor interrupts through external +interrupts (MEI) instead, then {\tt mip}.MSIP and {\tt mie}.MSIE may +both be hardwired to zeros. If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of {\tt mip} and SEIE, STIE, and SSIE of {\tt mie} are hardwired to zeros. |