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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-08-17 14:30:29 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-17 14:30:29 -0700 |
| commit | 010606fbd227838a95e0caf2b9d6f43376d62329 (patch) | |
| tree | 9ef49688a501a4ab7b4eeb1e3df0a6cbcee3b4df /src/machine.tex | |
| parent | 0aa4bcea7a9715c34e90cd246151f2b4968fbc19 (diff) | |
| download | riscv-isa-manual-010606fbd227838a95e0caf2b9d6f43376d62329.zip riscv-isa-manual-010606fbd227838a95e0caf2b9d6f43376d62329.tar.gz riscv-isa-manual-010606fbd227838a95e0caf2b9d6f43376d62329.tar.bz2 | |
Clarify priorities of synchronous exceptions (#715)
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 44 |
1 files changed, 30 insertions, 14 deletions
diff --git a/src/machine.tex b/src/machine.tex index 4618eef..ab4a21e 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2073,24 +2073,37 @@ The priority of any custom synchronous exceptions is implementation-defined. \begin{tabular}{|l|r|l|} \hline - Priority & Exception Code & Description \\ + Priority & Exc. Code & Description \\ + \hline + {\em Highest} & 3 & Instruction address breakpoint \\ + \hline + & & During instruction address translation: \\ + & 12, 1 & \quad First encountered page fault or + access fault \\ + \hline + & & With physical instruction address: \\ + & 1 & \quad Instruction access fault \\ \hline - {\em Highest} & 3 & Instruction address breakpoint \\ \hline - & 12 & Instruction page fault \\ \hline - & 1 & Instruction access fault \\ \hline & 2 & Illegal instruction \\ & 0 & Instruction address misaligned \\ & 8, 9, 11 & Environment call \\ & 3 & Environment break \\ - & 3 & Load/Store/AMO address breakpoint \\ \hline - {\em Optionally, these may have} - & 6 & Store/AMO address misaligned \\ - {\em lowest priority instead.} - & 4 & Load address misaligned \\ \hline - & 15 & Store/AMO page fault \\ - & 13 & Load page fault \\ \hline - & 7 & Store/AMO access fault \\ - & 5 & Load access fault \\ + & 3 & Load/store/AMO address breakpoint \\ + \hline + & & Optionally: \\ + & 4, 6 & \quad Load/store/AMO address misaligned \\ + \hline + & & During address translation for an explicit + memory access: \\ + & 5, 7, 13, 15 & \quad First encountered page fault or + access fault \\ + \hline + & & With physical address for an explicit + memory access: \\ + & 5, 7 & \quad Load/store/AMO access fault \\ + \hline + & & If not higher priority: \\ + {\em Lowest} & 4, 6 & \quad Load/store/AMO address misaligned \\ \hline \end{tabular} @@ -2099,7 +2112,10 @@ The priority of any custom synchronous exceptions is implementation-defined. \label{exception-priority} \end{table*} -Note that load/store/AMO address-misaligned exceptions may have +When address translation is performed, the address translation +algorithm determines what specific exception may be raised. + +Load/store/AMO address-misaligned exceptions may have either higher or lower priority than load/store/AMO page-fault and access-fault exceptions. \begin{commentary} |