Define the RV32-only medelegh CSR (#1109)

* Define the RV32-only medelegh CSR

* Define the RV32-only hedelegh CSR

1 files changed, 7 insertions, 2 deletions

diff --git a/src/machine.adoc b/src/machine.adoc
index 2160257..c98b128 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -1134,8 +1134,9 @@ appropriate level with the MRET instruction
 implementations can provide individual read/write bits within `medeleg`
 and `mideleg` to indicate that certain exceptions and interrupts should
 be processed directly by a lower privilege level. The machine exception
-delegation register (`medeleg`) and machine interrupt delegation
-register (`mideleg`) are MXLEN-bit read/write registers.
+delegation register (`medeleg`) is a 64-bit read/write register.
+The machine interrupt delegation register (`mideleg`) is an MXLEN-bit
+read/write register.
 
 In systems with S-mode, the `medeleg` and `mideleg` registers must
 exist, and setting a bit in `medeleg` or `mideleg` will delegate the
@@ -1203,6 +1204,10 @@ bit position equal to the value returned in the `mcause` register (i.e.,
 setting bit 8 allows user-mode environment calls to be delegated to a
 lower-privilege trap handler).
 
+When XLEN=32, `medelegh` is a 32-bit read/write register
+that aliases bits 63:32 of `medeleg`.
+Register `medelegh` does not exist when XLEN=64.
+
 .Machine Interrupt Delegation Register `mideleg`.
 include::images/bytefield/mideleg.adoc[]