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author | Bill Traynor <wmat@riscv.org> | 2023-01-03 15:09:56 -0500 |
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committer | Bill Traynor <wmat@riscv.org> | 2023-01-03 15:09:56 -0500 |
commit | 3f89bfe32cc2c0e77fa7a8b9e4a46f27f103a245 (patch) | |
tree | 668e31193175d366322d8c84bf23017124dda278 /src/m-st-ext.adoc | |
parent | dd72c724a173cbe14a33d8fc6d365e2cfa4afbcf (diff) | |
download | riscv-isa-manual-3f89bfe32cc2c0e77fa7a8b9e4a46f27f103a245.zip riscv-isa-manual-3f89bfe32cc2c0e77fa7a8b9e4a46f27f103a245.tar.gz riscv-isa-manual-3f89bfe32cc2c0e77fa7a8b9e4a46f27f103a245.tar.bz2 |
Adding in multiplicatin character.
Adding in multiplication character. Unicode U+00D7.
Diffstat (limited to 'src/m-st-ext.adoc')
-rw-r--r-- | src/m-st-ext.adoc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/m-st-ext.adoc b/src/m-st-ext.adoc index 051a9ca..78942ff 100644 --- a/src/m-st-ext.adoc +++ b/src/m-st-ext.adoc @@ -1,8 +1,8 @@ [[mstandard]] -== M Standard Extension for Integer Multiplication and Division, Version 2.0 +== "M" Standard Extension for Integer Multiplication and Division, Version 2.0 This chapter describes the standard integer multiplication and division -instruction extension, which is named M and contains instructions +instruction extension, which is named "M" and contains instructions that multiply or divide values held in two integer registers. [TIP] @@ -22,12 +22,12 @@ include::images/wavedrom/m-st-ext-for-int-mult.adoc[] (((MUL, MULHU))) (((MUL, MULHSU))) -MUL performs an XLEN-bit`x`XLEN-bit multiplication of +MUL performs an XLEN-bit×XLEN-bit multiplication of _rs1_ by _rs2_ and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but -return the upper XLEN bits of the full 2`x`XLEN-bit -product, for signed 'x' signed, -unsigned 'x' unsigned, and _rs1_`x` unsigned _rs2_ multiplication, respectively. +return the upper XLEN bits of the full 2×XLEN-bit +product, for signed × signed, +unsigned × unsigned, and _rs1_× unsigned _rs2_ multiplication, respectively. If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] _rdh, rs1, rs2_; MUL _rdl, rs1, rs2_ (source register specifiers must be in same order and _rdh_ cannot be the same as _rs1_ or _rs2_). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies. [NOTE] |