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author | elisa <elisa@riscv.org> | 2021-10-22 11:25:16 -0700 |
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committer | elisa <elisa@riscv.org> | 2021-10-22 11:25:16 -0700 |
commit | f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d (patch) | |
tree | 0ce6ae0478d3ad3b20f42131a7e80788c9876e41 /src/images | |
parent | a4954af2fd406e6f7fb9a1925d5b870c6bb155ec (diff) | |
download | riscv-isa-manual-f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d.zip riscv-isa-manual-f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d.tar.gz riscv-isa-manual-f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d.tar.bz2 |
table and diagram fixes, added some missing c diagrams
Diffstat (limited to 'src/images')
24 files changed, 106 insertions, 74 deletions
diff --git a/src/images/f-standard.png b/src/images/f-standard.png Binary files differdeleted file mode 100644 index 9a0a2c1..0000000 --- a/src/images/f-standard.png +++ /dev/null diff --git a/src/images/wavedrom/atomic-mem.adoc b/src/images/wavedrom/atomic-mem.adoc index 65c3f88..7132ddd 100644 --- a/src/images/wavedrom/atomic-mem.adoc +++ b/src/images/wavedrom/atomic-mem.adoc @@ -1,15 +1,19 @@ //## 9.4 Atomic Memory Operations -[wavedrom, .svg] + + +[wavedrom, ,] .... {reg: [ - {bits: 7, name: 'opcode', attr: 'AMO', type: 8}, - {bits: 5, name: 'rd', attr: 'dest', type: 2}, - {bits: 3, name: 'func3', attr: 'width', type: 8}, - {bits: 5, name: 'rs1', attr: 'addr', type: 4}, - {bits: 5, name: 'rs2', attr: ['0', 'src'], type: 4}, - {bits: 1, name: 'rl', type: 8}, - {bits: 1, name: 'aq', type: 8}, - {bits: 5, name: 'funct5', attr: ['AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D', 'AMOMIN[U].W/D'], type: 8}, -]} + {bits: 7, name: 'opcode', type: 8, attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']}, + {bits: 5, name: 'rd', type: 2, attr: ['5','dest','dest','dest','dest','dest','dest','dest']}, + {bits: 3, name: 'func3', type: 8, attr: ['3','width','width','width','width','width','width','width']}, + {bits: 5, name: 'rs1`', type: 4, attr: ['5','addr','addr','addr','addr','addr','addr','addr']}, + {bits: 5, name: 'rs2', type: 4, attr: ['5','src','src','src','src','src','src','src']}, + {bits: 1, name: 'rl', type: 8, attr: ['1','or', 'd', 'er', 'i', 'n', 'g']}, + {bits: 1, name: 'aq', type: 8, attr: ['1','or', 'd', 'er', 'i', 'n', 'g']}, + {bits: 6, name: 'funct5', type: 8, attr: ['5','AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D','AMOMIN[U].W/D']}, +], config: {bits: 32}} .... + + diff --git a/src/images/wavedrom/c-cj-format-ls.adoc b/src/images/wavedrom/c-cj-format-ls.adoc new file mode 100644 index 0000000..fcb5c7a --- /dev/null +++ b/src/images/wavedrom/c-cj-format-ls.adoc @@ -0,0 +1,23 @@ +//c-cj-format-ls + +//[wavedrom, ,svg] +//.... +//{reg: [ +// {bits: 2, name: 'op', type: 4, attr: ['2','CI','CI']}, +// {bits: 10, name: 'imm', type: 2, }, +// {bits: 4, name: 'funct3' type: 4, attr:['3','CJ','CJAL']}, +//] config: {bits: 16}} +//.... + + +[wavedrom, , svg] +.... +{reg: [ + {bits: 2, name: 'op', type: 8, attr: ['2','CI','CI']}, + {bits: 11, name: 'imm', type: 2, attr: ['11','offset[11|4|9:8|10|6|7|3:1|5]','offset[11|4|9:8|10|6|7|3:1|5]']}, + {bits: 3, name: 'funct3', type: 8, attr: ['3','CJ','CJAL']}, +], config: {bits: 16}} +.... + + + diff --git a/src/images/wavedrom/c-cs-format-ls.adoc b/src/images/wavedrom/c-cs-format-ls.adoc new file mode 100644 index 0000000..8c1db1b --- /dev/null +++ b/src/images/wavedrom/c-cs-format-ls.adoc @@ -0,0 +1,16 @@ +//## 16.X Load and Store Instructions +//### c-cs-format-ls + +[wavedrom, ,] +.... +{reg: [ + {bits: 2, name: 'op', type: 8, attr: ['C0','C0','C0','C0','C0']}, + {bits: 3, name: 'rs2`', type: 3, attr: ['src','src','src','src','src']}, + {bits: 2, name: 'imm', type: 2, attr: ['offset[2|6]','offset[7:6]','offset[7:6]','offset[2|6]','offset[7:6]']}, + {bits: 3, name: 'rs1`', type: 3, attr: ['base','base','base','base','base']}, + {bits: 3, name: 'imm', types:3, attr: ['offset[5:3]','offset[5:3]','offset[5|4|8]','offset[5:3]','offset[5:3]']}, + {bits: 3, name: 'funct3', type: 8, attr: ['C.SW','C.SD','C.SQ','C.FSW','C.FSD']}, +], config: {bits: 16}} +.... + + diff --git a/src/images/wavedrom/c-sp-load-store-css.adoc b/src/images/wavedrom/c-sp-load-store-css.adoc new file mode 100644 index 0000000..8bbe0d9 --- /dev/null +++ b/src/images/wavedrom/c-sp-load-store-css.adoc @@ -0,0 +1,14 @@ +//c-sp load and store, css format--is this correct? + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'op', type: 8, attr: ['2','C2','C2','C2','C2','C2']}, + {bits: 5, name: 'rs2', type: 4, attr: ['5','src', 'src', 'src', 'src', 'src']}, + {bits: 6, name: 'imm', type: 3, attr: ['6','offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']}, + {bits: 4, name: 'funct3', type: 8, attr: ['3','C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']}, +], config: {bits: 16}} +.... + + + diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.adoc index 4defc62..b656a42 100644 --- a/src/images/wavedrom/c-sp-load-store.adoc +++ b/src/images/wavedrom/c-sp-load-store.adoc @@ -1,27 +1,14 @@ //## 16.3 Load and Store Instructions //### Stack-Pointer-Based Loads and Stores -[wavedrom, , svg] +[wavedrom, ,] .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['C2','C2','C2','C2','C2']}, - {bits: 5, name: 'imm', type: 5, attr: ['offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']}, - {bits: 5, name: 'rd', type: 5, attr: ['dest ࣔ 0', 'dest ≠ 0', 'dest ≠ 0', 'dest', 'dest']}, - {bits: 1, name: 'imm', type: 1, attr: ['offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']}, - {bits: 3, name: 'funct3', type: 3, attr: ['C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']}, -], config: {bits: 16}} -.... - - - -[wavedrom, , svg] -.... -{reg: [ - {bits: 1, name: 'op', type: 8, attr: ['C2','C2','C2','C2','C2']}, - {bits: 5, name: 'imm', type: 2, attr: ['offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']}, - {bits: 5, name: 'rd', type: 3, attr: ['dest ≠ 0','dest ≠ 0','dest ≠ 0','dest','dest']}, - {bits: 1, name: 'imm', types:3, attr: ['offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']}, - {bits: 4, name: 'funct3', type: 8, attr: ['C.LWSP','C.LDSP','C.LQSP','C.FLWSP','C.FLDSP']}, + {bits: 2, name: 'op', type: 8, attr: ['2','C2','C2','C2','C2','C2']}, + {bits: 5, name: 'imm', type: 5, attr: ['5','offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']}, + {bits: 5, name: 'rd', type: 5, attr: ['5','dest latexmath:[$\neq$] 0', 'dest latexmath:[$\neq$] 0', 'dest latexmath:[$\neq$] 0', 'dest', 'dest']}, + {bits: 1, name: 'imm', type: 1, attr: ['1','offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']}, + {bits: 3, name: 'funct3', type: 3, attr: ['3','C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.adoc index 60c6d54..299c93b 100644 --- a/src/images/wavedrom/cr-register.adoc +++ b/src/images/wavedrom/cr-register.adoc @@ -3,7 +3,7 @@ //Table 16.1: Compressed 16-bit RVC instruction formats. //### CR : Register -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 2, name: 'op', type: 8}, diff --git a/src/images/wavedrom/d-xwwx.adoc b/src/images/wavedrom/d-xwwx.adoc index 913da9a..e50553c 100644 --- a/src/images/wavedrom/d-xwwx.adoc +++ b/src/images/wavedrom/d-xwwx.adoc @@ -1,6 +1,6 @@ //xw-wx -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/double-fl-class.adoc b/src/images/wavedrom/double-fl-class.adoc index b57aa8f..afd8021 100644 --- a/src/images/wavedrom/double-fl-class.adoc +++ b/src/images/wavedrom/double-fl-class.adoc @@ -1,6 +1,6 @@ //## 13.7 Double-Precision Floating-Point Classify Instruction -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/double-fl-compare.adoc b/src/images/wavedrom/double-fl-compare.adoc index 51f70d9..bd12aab 100644 --- a/src/images/wavedrom/double-fl-compare.adoc +++ b/src/images/wavedrom/double-fl-compare.adoc @@ -1,6 +1,6 @@ //## 13.6 Double-Precision Floating-Point Compare Instructions -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/double-fl-compute.adoc b/src/images/wavedrom/double-fl-compute.adoc index 96251e8..9b2640b 100644 --- a/src/images/wavedrom/double-fl-compute.adoc +++ b/src/images/wavedrom/double-fl-compute.adoc @@ -1,6 +1,6 @@ //## 13.4 Double-Precision Floating-Point Computational Instructions -[wavedrom, , svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, @@ -13,7 +13,7 @@ ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, @@ -26,7 +26,7 @@ ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, @@ -39,7 +39,7 @@ ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, diff --git a/src/images/wavedrom/double-fl-convert-mv.adoc b/src/images/wavedrom/double-fl-convert-mv.adoc index ac6d7e6..055b9f1 100644 --- a/src/images/wavedrom/double-fl-convert-mv.adoc +++ b/src/images/wavedrom/double-fl-convert-mv.adoc @@ -1,7 +1,7 @@ //## 13.5 Double-Precision Floating-Point Conversion and Move Instructions -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/double-ls.adoc b/src/images/wavedrom/double-ls.adoc index b7d6b87..42200ab 100644 --- a/src/images/wavedrom/double-ls.adoc +++ b/src/images/wavedrom/double-ls.adoc @@ -1,7 +1,7 @@ //# "D" Standard Extension for Double-Precision Floating-Point, Version 2.2 //## 13.3 Double-Precision Load and Store Instructions -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'LOAD-FP', type: 8}, @@ -12,7 +12,7 @@ ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'STORE-FP', type: 8}, diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc b/src/images/wavedrom/fcvt-sd-ds.adoc index 085f300..22a47f0 100644 --- a/src/images/wavedrom/fcvt-sd-ds.adoc +++ b/src/images/wavedrom/fcvt-sd-ds.adoc @@ -1,6 +1,6 @@ //FCVT.S.D and FCVT.D.S -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc b/src/images/wavedrom/fsjgnjnx-d.adoc index 5e4ca6c..8972c06 100644 --- a/src/images/wavedrom/fsjgnjnx-d.adoc +++ b/src/images/wavedrom/fsjgnjnx-d.adoc @@ -1,6 +1,6 @@ //FSGNJ.D, FSGNJN.D, and FSGNJX.D -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/half-ls.adoc b/src/images/wavedrom/half-ls.adoc index 41ecfaa..2732863 100644 --- a/src/images/wavedrom/half-ls.adoc +++ b/src/images/wavedrom/half-ls.adoc @@ -1,6 +1,6 @@ //## 15.1 Half-Precision Load and Store Instructions -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'LOAD-FP', type: 8}, diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc index 37cd9e3..a03ffec 100644 --- a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc +++ b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc @@ -1,6 +1,6 @@ //quad-cnvrt-intch-xqqx -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/quad-cnvrt-mv.adoc b/src/images/wavedrom/quad-cnvrt-mv.adoc index 7062f18..eada735 100644 --- a/src/images/wavedrom/quad-cnvrt-mv.adoc +++ b/src/images/wavedrom/quad-cnvrt-mv.adoc @@ -1,6 +1,6 @@ //## 14.3 Quad-Precision Convert and Move Instructions -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, @@ -13,7 +13,7 @@ ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/quad-compute.adoc b/src/images/wavedrom/quad-compute.adoc index 88ddb61..ff0d36a 100644 --- a/src/images/wavedrom/quad-compute.adoc +++ b/src/images/wavedrom/quad-compute.adoc @@ -1,6 +1,6 @@ //## 14.2 Quad-Precision Computational Instructions -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, @@ -13,7 +13,7 @@ ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, @@ -26,7 +26,7 @@ ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, @@ -40,7 +40,7 @@ .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, diff --git a/src/images/wavedrom/quad-float-clssfy.adoc b/src/images/wavedrom/quad-float-clssfy.adoc index 8b276c8..526cb54 100644 --- a/src/images/wavedrom/quad-float-clssfy.adoc +++ b/src/images/wavedrom/quad-float-clssfy.adoc @@ -1,6 +1,6 @@ //## 14.5 Quad-Precision Floating-Point Classify Instruction -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/quad-float-compare.adoc b/src/images/wavedrom/quad-float-compare.adoc index 0a4e2b7..c94b369 100644 --- a/src/images/wavedrom/quad-float-compare.adoc +++ b/src/images/wavedrom/quad-float-compare.adoc @@ -1,6 +1,6 @@ //## 14.4 Quad-Precision Floating-Point Compare Instructions -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, diff --git a/src/images/wavedrom/quad-ls.adoc b/src/images/wavedrom/quad-ls.adoc index 7cb2799..90654ab 100644 --- a/src/images/wavedrom/quad-ls.adoc +++ b/src/images/wavedrom/quad-ls.adoc @@ -1,6 +1,6 @@ //## 14.1 Quad-Precision Load and Store Instructions -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'LOAD-FP', type: 8}, @@ -11,7 +11,7 @@ ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'STORE-FP', type: 8}, diff --git a/src/images/wavedrom/reg-based-ldnstr.adoc b/src/images/wavedrom/reg-based-ldnstr.adoc index d073697..818f203 100644 --- a/src/images/wavedrom/reg-based-ldnstr.adoc +++ b/src/images/wavedrom/reg-based-ldnstr.adoc @@ -1,14 +1,15 @@ //Register-Based loads and Stores -//needs fix -[wavedrom, ,svg] + +[wavedrom, ,] .... {reg: [ {bits: 2, name: 'op', attr: ['2', 'CD', 'CD', 'CD', 'CD', 'CD'], type: 8}, - {bits: 4, name: 'rd', attr: ['3', 'dest', 'dest','dest','dest','dest'], type: 3}, + {bits: 3, name: 'rd`', attr: ['3', 'dest', 'dest','dest','dest','dest'], type: 3}, {bits: 2, name: 'imm', attr:['2', 'offest[2|6]', 'offest[7:6]', 'offest[7:6]', 'offest[2|6]', 'offest[7:6]'], type: 2}, - {bits: 4, name: 'rs2 `', attr: ['3', 'base', 'base', 'base', 'base', 'base'], type: 2}, - {bits: 4, name: 'imm', attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]'], type: 3}, - {bits: 4, name: 'funct3', attr: ['3', 'C|W', 'C|D', 'C|Q', 'CF|W', 'CF|D'], type: 8}, -]} + {bits: 3, name: 'rs1`', attr: ['3', 'base', 'base', 'base', 'base', 'base'], type: 2}, + {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]'], type: 3}, + {bits: 3, name: 'funct3', attr: ['3', 'C|W', 'C|D', 'C|Q', 'CF|W', 'CF|D'], type: 8}, +], config: {bits: 16}} .... + diff --git a/src/images/wavedrom/sp-base-ls-2.adoc b/src/images/wavedrom/sp-base-ls-2.adoc deleted file mode 100644 index 69ee285..0000000 --- a/src/images/wavedrom/sp-base-ls-2.adoc +++ /dev/null @@ -1,13 +0,0 @@ - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: 'op', type: 8, attr: ['C2','C2','C2','C2','C2']}, - {bits: 5, name: 'rs2', type: 4, attr: ['src', 'src', 'src', 'src', 'src']}, - {bits: 6, name: 'imm', type: 3, attr: ['offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']}, - {bits: 3, name: 'funct3', type: 8, attr: ['C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']}, -], config: {bits: 16}} -.... - - - |