adding build images and wavedrom source files

45 files changed, 1034 insertions, 0 deletions

diff --git a/src/images/backpage.png b/src/images/backpage.png
new file mode 100644
index 0000000..cc4317d
--- /dev/null
+++ b/src/images/backpage.png
diff --git a/src/images/base-unpriv-reg-state.png b/src/images/base-unpriv-reg-state.png
new file mode 100644
index 0000000..6ee8589
--- /dev/null
+++ b/src/images/base-unpriv-reg-state.png
diff --git a/src/images/risc-v_logo.png b/src/images/risc-v_logo.png
new file mode 100644
index 0000000..d754746
--- /dev/null
+++ b/src/images/risc-v_logo.png
diff --git a/src/images/wavedrom/atomic-mem.adoc b/src/images/wavedrom/atomic-mem.adoc
new file mode 100644
index 0000000..65c3f88
--- /dev/null
+++ b/src/images/wavedrom/atomic-mem.adoc
@@ -0,0 +1,15 @@
+//## 9.4 Atomic Memory Operations
+
+[wavedrom, .svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'AMO', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: 'width', type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'addr', type: 4},
+  {bits: 5,  name: 'rs2',       attr: ['0', 'src'], type: 4},
+  {bits: 1,  name: 'rl', type: 8},
+  {bits: 1,  name: 'aq', type: 8},
+  {bits: 5,  name: 'funct5', attr: ['AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D', 'AMOMIN[U].W/D'], type: 8},
+]}
+....
diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.adoc
new file mode 100644
index 0000000..2762d9b
--- /dev/null
+++ b/src/images/wavedrom/c-sp-load-store.adoc
@@ -0,0 +1,14 @@
+//## 16.3 Load and Store Instructions
+//### Stack-Pointer-Based Loads and Stores
+
+[wavedrom, , svg]
+....
+{reg: [
+  {bits: 2, name: 'op',     type: 8, attr: 'C2'},
+  {bits: 5, name: 'imm',    type: 3, attr: ['offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']},
+  {bits: 5, name: 'rd',     type: 2, attr: ['dest ≠ 0', 'dest ≠ 0', 'dest ≠ 0', 'dest', 'dest']},
+  {bits: 1, name: 'imm',    type: 3, attr: 'offset[5]'},
+  {bits: 3, name: 'funct3', type: 8, attr: ['C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']},
+], config: {bits: 16}}
+....
+
diff --git a/src/images/wavedrom/counters-diag.adoc b/src/images/wavedrom/counters-diag.adoc
new file mode 100644
index 0000000..ea9858d
--- /dev/null
+++ b/src/images/wavedrom/counters-diag.adoc
@@ -0,0 +1,14 @@
+//# 11 Counters
+//## 11.1 Base Counters and Timers
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: 'SYSTEM',  type: 8},
+  {bits: 5,  name: 'rd',     attr: 'dest',    type: 2},
+  {bits: 3,  name: 'func3',  attr: 'CSRRS',   type: 8},
+  {bits: 5,  name: 'rs1',    attr: 0,         type: 8},
+  {bits: 12, name: 'csr',    attr: ['RDCYCLE[H]', 'RDTIME[H]', 'RDINSTRET[H]'], type: 4},
+]}
+....
+
diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.adoc
new file mode 100644
index 0000000..88db337
--- /dev/null
+++ b/src/images/wavedrom/cr-register.adoc
@@ -0,0 +1,74 @@
+//# 16 "C" Standard Extension for Compressed Instructions, Version 2.0
+//## 16.2 Compressed Instruction Formats
+//Table 16.1: Compressed 16-bit RVC instruction formats.
+//### CR : Register
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op',     type: 8},
+  {bits: 5, name: 'rs2',    type: 4},
+  {bits: 5, name: 'rd / rs1', type: 7},
+  {bits: 4, name: 'funct4', type: 8},
+
+  {bits: 2, name: 'op',     type: 8},
+  {bits: 5, name: 'imm',    type: 3},
+  {bits: 5, name: 'rd / rs1', type: 7},
+  {bits: 1, name: 'imm',    type: 3},
+  {bits: 3, name: 'funct3', type: 8},
+
+  {bits: 2, name: 'op',     type: 8},
+  {bits: 5, name: 'rs2',    type: 4},
+  {bits: 6, name: 'imm',    type: 3},
+  {bits: 3, name: 'funct3', type: 8},
+
+  {bits: 2, name: 'op',     type: 8},
+  {bits: 3, name: 'rd`',    type: 2},
+  {bits: 8, name: 'imm',    type: 3},
+  {bits: 3, name: 'funct3', type: 8},
+
+  {bits: 2, name: 'op',     type: 8},
+  {bits: 3, name: 'rd`',    type: 2},
+  {bits: 2, name: 'imm',    type: 3},
+  {bits: 3, name: 'rs1`',   type: 4},
+  {bits: 3, name: 'imm',    type: 3},
+  {bits: 3, name: 'funct3', type: 8},
+
+  {bits: 2, name: 'op',     type: 8},
+  {bits: 3, name: 'rs2`',   type: 4},
+  {bits: 2, name: 'imm',    type: 3},
+  {bits: 3, name: 'rs1`',   type: 4},
+  {bits: 3, name: 'imm',    type: 3},
+  {bits: 3, name: 'funct3', type: 8},
+
+  {bits: 2, name: 'op',     type: 8},
+  {bits: 3, name: 'rs2`',   type: 4},
+  {bits: 2, name: 'funct2', type: 8},
+  {bits: 3, name: 'rd` / rs1`',   type: 7},
+  {bits: 6, name: 'funct6', type: 8},
+
+  {bits: 2, name: 'op',     type: 8},
+  {bits: 5, name: 'offset', type: 3},
+  {bits: 3, name: 'rd` / rs1`',   type: 7},
+  {bits: 3, name: 'offset', type: 3},
+  {bits: 3, name: 'funct3', type: 8},
+
+  {bits: 2,  name: 'op',     type: 8},
+  {bits: 11, name: 'jump target', type: 3},
+  {bits: 3,  name: 'funct3', type: 8},
+],
+
+}
+....
+
+//the following configuration broke the build.
+//config: {
+//  hflip: true,
+//  compact: true,
+//  bits: 16 * 9, lanes: 9,
+//  margin: {right: width / 4},
+// label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS : Store', 'CA : //Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']}
+//}
+
+
+
diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.adoc
new file mode 100644
index 0000000..f42bce0
--- /dev/null
+++ b/src/images/wavedrom/csr-instr.adoc
@@ -0,0 +1,24 @@
+//# 10 "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
+//## 10.1 CSR Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: 'SYSTEM',      type: 8},
+  {bits: 5,  name: 'rd',     attr: 'dest',        type: 2},
+  {bits: 3,  name: 'func3',  attr: ['CSRRW', 'CSRRS', 'CSRRC'], type: 8},
+  {bits: 5,  name: 'rs1',    attr: 'source',      type: 4},
+  {bits: 12, name: 'csr',    attr: 'source/dest', type: 4},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: 'SYSTEM',      type: 8},
+  {bits: 5,  name: 'rd',     attr: 'dest',        type: 2},
+  {bits: 3,  name: 'func3',  attr: ['CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8},
+  {bits: 5,  name: 'rs1',    attr: 'uimm[4:0]',   type: 3},
+  {bits: 12, name: 'csr',    attr: 'source/dest', type: 4},
+]}
+....
diff --git a/src/images/wavedrom/ct-conditional.adoc b/src/images/wavedrom/ct-conditional.adoc
new file mode 100644
index 0000000..f7f782e
--- /dev/null
+++ b/src/images/wavedrom/ct-conditional.adoc
@@ -0,0 +1,15 @@
+//### Conditional Branches
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'BRANCH', type: 8},
+  {bits: 1,  name: '[11]',      type: 3},
+  {bits: 4,  name: 'imm[4:1]',  attr: 'offset', type: 3},
+  {bits: 3,  name: 'func3',     attr: ['BEQ', 'BNE', 'BLT', 'BLTU', 'BGE', 'BGEU'], type: 8},
+  {bits: 5,  name: 'rs1', attr: 'src1', type: 4},
+  {bits: 5,  name: 'rs2', attr: 'src2', type: 4},
+  {bits: 6,  name: 'imm[10:5]', attr: 'offset', type: 3},
+  {bits: 1,  name: '[12]',      type: 3},
+]}
+....
diff --git a/src/images/wavedrom/ct-unconditional-2.adoc b/src/images/wavedrom/ct-unconditional-2.adoc
new file mode 100644
index 0000000..4ed18da
--- /dev/null
+++ b/src/images/wavedrom/ct-unconditional-2.adoc
@@ -0,0 +1,12 @@
+//ct-unconditional-2
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',     attr: 'JALR', type: 8},
+  {bits: 5,  name: 'rd',         attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',      attr: 0, type: 8},
+  {bits: 5,  name: 'rs1',        attr: 'base', type: 4},
+  {bits: 12, name: 'imm[11:0]',  attr: 'offset', type: 3},
+]}
+....
diff --git a/src/images/wavedrom/ct-unconditional.adoc b/src/images/wavedrom/ct-unconditional.adoc
new file mode 100644
index 0000000..67a590c
--- /dev/null
+++ b/src/images/wavedrom/ct-unconditional.adoc
@@ -0,0 +1,15 @@
+//## 2.5 Control Transfer Instructions
+//### Unconditional Jumps
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',     attr: 'JAL', type: 8},
+  {bits: 5,  name: 'rd',         attr: 'dest', type: 2},
+  {bits: 8,  name: 'imm[19:12]', type: 3},
+  {bits: 1,  name: '[11]',    type: 3, attr: 'offset'},
+  {bits: 10, name: 'imm[10:1]',  type: 3},
+  {bits: 1,  name: '[20]',    type: 3},
+]}
+....
+
diff --git a/src/images/wavedrom/division-op.adoc b/src/images/wavedrom/division-op.adoc
new file mode 100644
index 0000000..8d2f446
--- /dev/null
+++ b/src/images/wavedrom/division-op.adoc
@@ -0,0 +1,25 @@
+//## 8.2 Division Operations
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: 'OP',            type: 8},
+  {bits: 5,  name: 'rd',     attr: 'dest',          type: 2},
+  {bits: 3,  name: 'func3',  attr: ['DIV', 'DIVU', 'REM', 'REMU'], type: 8},
+  {bits: 5,  name: 'rs1',    attr: 'dividend',      type: 4},
+  {bits: 5,  name: 'rs2',    attr: 'divisor',       type: 4},
+  {bits: 7,  name: 'funct7', attr: 'MULDIV',        type: 8},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: 'OP-32',         type: 8},
+  {bits: 5,  name: 'rd',     attr: 'dest',          type: 2},
+  {bits: 3,  name: 'func3',  attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW'],          type: 8},
+  {bits: 5,  name: 'rs1',    attr: 'dividend',      type: 4},
+  {bits: 5,  name: 'rs2',    attr: 'divisor',       type: 4},
+  {bits: 7,  name: 'funct7', attr: 'MULDIV',        type: 8},
+]}
+....
diff --git a/src/images/wavedrom/env_call-breakpoint.adoc b/src/images/wavedrom/env_call-breakpoint.adoc
new file mode 100644
index 0000000..d76947a
--- /dev/null
+++ b/src/images/wavedrom/env_call-breakpoint.adoc
@@ -0,0 +1,12 @@
+//## 2.8 Environment Call and Breakpoints
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'SYSTEM', type: 8},
+  {bits: 5,  name: 'rd',    attr: 0},
+  {bits: 3,  name: 'func3', attr: 'PRIV', type: 8},
+  {bits: 5,  name: 'rs1',   attr: 0},
+  {bits: 12, name: 'func12', attr: ['ECALL', 'EBREAK'], type: 8},
+]}
+....
diff --git a/src/images/wavedrom/float-csr.adoc b/src/images/wavedrom/float-csr.adoc
new file mode 100644
index 0000000..19ca39c
--- /dev/null
+++ b/src/images/wavedrom/float-csr.adoc
@@ -0,0 +1,17 @@
+//# "F" Standard Extension for Single-Precision Floating-Point, Version 2.2
+//## 12.2 Floating-Point Control and Status Register
+//### Figure 12.2: Floating-point control and status register.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: 'NX'},
+  {bits: 1,  name: 'UF'},
+  {bits: 1,  name: 'OF'},
+  {bits: 1,  name: 'DZ'},
+  {bits: 1,  name: 'NV'},
+  {bits: 3,  name: 'frm'},
+  {bits: 24},
+]}
+....
+
diff --git a/src/images/wavedrom/fnmaddsub.adoc b/src/images/wavedrom/fnmaddsub.adoc
new file mode 100644
index 0000000..6c6a27d
--- /dev/null
+++ b/src/images/wavedrom/fnmaddsub.adoc
@@ -0,0 +1,16 @@
+
+//FNMSUP and FNMADD
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'],    type: 8},
+  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
+  {bits: 3, name: 'func3',  attr: 'RM', type: 8},
+  {bits: 5, name: 'rs1',    attr: 'src1',     type: 4},
+  {bits: 5, name: 'rs2',    attr: 'src2',     type: 4},
+  {bits: 2, name: 'fmt',    attr: 'S',        type: 8},
+  {bits: 5, name: 'rs3',    attr: 'src3',     type: 4},
+]}
+....
+
diff --git a/src/images/wavedrom/hint-nopv_rv32i.adoc b/src/images/wavedrom/hint-nopv_rv32i.adoc
new file mode 100644
index 0000000..3303bd5
--- /dev/null
+++ b/src/images/wavedrom/hint-nopv_rv32i.adoc
@@ -0,0 +1,55 @@
+//### RV32I
+//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (2.9)
+//{ADDI, SLTI, SLTIU, XORI, ORI, ANDI} x0, ? ( ${ 6 * 1 << 17} )
+[wavedrom, ,svg]
+....
+{reg: [
+    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
+    {name: 'rd',     bits: 5, attr: 0},
+    {name: 'func3',  bits: 3, attr: ['ADDI', 'SLTI', 'SLTIU', 'XORI', 'ORI', 'ANDI']},
+    {bits: 17}
+], config: {hspace: width}}
+....
+//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
+
+[wavedrom, ,svg]
+....
+{reg:[
+    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
+    {name: 'rd',     bits: 5, attr: 0},
+    {name: 'func3',  bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
+    {bits: 10},
+    {name: 'imm?',   bits: 7, attr: [0, 0, 32]}
+], config: {hspace: width}}
+....
+//{LUI, AUIPC} x0, ? ( ${ 2 * (1 << 20) } )
+
+[wavedrom, ,svg]
+....
+{reg:[
+    {name: 'opcode', bits: 7,  attr: ['AUIPC', 'LUI']},
+    {name: 'rd',     bits: 5,  attr: 0},
+    {bits: 20}
+], config: {hspace: width}}
+....
+//{ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND} x0, ?, ? ( ${ 10 * 1 << 10} )
+
+[wavedrom, ,svg]
+....
+{reg:[
+    {name: 'OP',     bits: 7, attr: 0b0110011},
+    {name: 'rd',     bits: 5, attr: 0},
+    {name: 'func3',  bits: 3, attr: 'ADD SUB SLL SLT SLTU XOR SRL SRA OR AND'.split(' ',
+    {bits: 10},
+    {name: 'func7',  bits: 7, attr: [0, 0, 0, 0, 0, 0, 32, 32, 0, 0]}
+], config: {hspace: width}}
+....
+
+//RV32I_extra = (
+//  3 * 31 +
+//  31 +
+//  7 * 31 +
+//  3 * 31 +
+//  2 * 31
+//)
+
diff --git a/src/images/wavedrom/hint-nopv_rv64i.adoc b/src/images/wavedrom/hint-nopv_rv64i.adoc
new file mode 100644
index 0000000..cafbc2e
--- /dev/null
+++ b/src/images/wavedrom/hint-nopv_rv64i.adoc
@@ -0,0 +1,57 @@
+//### RV64I
+//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (4.4)
+//All RV32I NOPs plus:
+//ADDIW x0, ? ( ${ 1 << 17 } )
+[wavedrom, ,svg]
+....
+{reg:[
+    {name: 'OP-IMM-32', bits: 7,  attr: 0b0011011},
+    {name: 'rd',     bits: 5,  attr: 0},
+    {name: 'func3',  bits: 3,  attr: 'ADDIW'},
+    {bits: 17}
+], config: {hspace: width}}
+....
+//Extra bit for the shift ammont:
+//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
+
+[wavedrom, ,svg]
+....
+{reg: [
+    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
+    {name: 'rd',     bits: 5, attr: 0},
+    {name: 'func3',  bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
+    {bits: 10},
+    {name: 'imm?',   bits: 7, attr: [1, 33, 33]}
+], config: {hspace: width}}
+....
+//{SLLIW, SRLIW, SRAIW} x0, ?( ${ 3 * 1 << 10} )
+
+[wavedrom, ,svg]
+....
+{reg:[
+    {name: 'OP-IMM-32', bits: 7,  attr: 0b0011011},
+    {name: 'rd',     bits: 5,  attr: 0},
+    {name: 'func3',  bits: 3,  attr: ['SLLIW', 'SRLIW', 'SRAIW']},
+    {bits: 10},
+    {name: 'imm?',   bits: 7, attr: [0, 32, 32]}
+], config: {hspace: width}}
+....
+//SLL, SLT, SRA ( ??? )
+//{ADDW, SLLW, SRLW, SUBW, SRAW} x0, ?, ? ( ${ 5 * 1 << 10 } )
+
+[wavedrom, ,svg]
+....
+{reg:[
+    {name: 'OP-32', bits: 7,  attr: 0b0111011},
+    {name: 'rd',     bits: 5,  attr: 0},
+    {name: 'func3',  bits: 3, attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']},
+    {bits: 10},
+    {name: 'func7',  bits: 7, attr: [0, 0, 32, 0, 32]}
+], config: {hspace: width}}
+....
+
+//RV64I_extra = (
+//  4 * 31 +
+//  5 * 31 +
+//  31
+//`
diff --git a/src/images/wavedrom/immediate.adoc b/src/images/wavedrom/immediate.adoc
new file mode 100644
index 0000000..206db02
--- /dev/null
+++ b/src/images/wavedrom/immediate.adoc
@@ -0,0 +1,60 @@
+//### Figure 2.4
+//Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31].
+//#### I-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: '[20]'},
+  {bits: 4,  name: '[24:21]'},
+  {bits: 6,  name: '[30:25]'},
+  {bits: 21,  name: '— [31] —', type: 7},
+]}
+....
+//#### S-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: '[7]'},
+  {bits: 4,  name: '[11:8]'},
+  {bits: 6,  name: '[30:25]'},
+  {bits: 21,  name: '— [31] —', type: 7},
+]}
+....
+//#### B-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: 'zero', type: 5},
+  {bits: 4,  name: '[11:8]'},
+  {bits: 6,  name: '[30:25]'},
+  {bits: 1,  name: '[7]'},
+  {bits: 20, name: '— [31] —', type: 7},
+]}
+....
+//#### U-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 12, name: 'zero', type: 5},
+  {bits: 8,  name: '[19:12]'},
+  {bits: 11, name: '[30:20]'},
+  {bits: 1,  name: '[31]', type: 7},
+]}
+....
+//#### J-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: 'zero', type: 5},
+  {bits: 4,  name: '[24:21]'},
+  {bits: 6,  name: '[30:25]'},
+  {bits: 1,  name: '[20]'},
+  {bits: 8,  name: '[19:12]'},
+  {bits: 12, name: '— [31] —', type: 7},
+]}
+....
diff --git a/src/images/wavedrom/immediate_variants.adoc b/src/images/wavedrom/immediate_variants.adoc
new file mode 100644
index 0000000..85b4ef4
--- /dev/null
+++ b/src/images/wavedrom/immediate_variants.adoc
@@ -0,0 +1,75 @@
+//## 2.3 Immediate Encoding Variants
+//### Figure 2.3
+//RISC-V base instruction formats showing immediate variants.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'rd'},
+  {bits: 3,  name: 'func3'},
+  {bits: 5,  name: 'rs1'},
+  {bits: 5,  name: 'rs2'},
+  {bits: 7,  name: 'funct7'}
+], config: {label: {right: 'R-Type'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'rd'},
+  {bits: 3,  name: 'func3'},
+  {bits: 5,  name: 'rs1'},
+  {bits: 12, name: 'imm[11:0]', type: 3},
+], config: {label: {right: 'I-Type'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'imm[4:0]', type: 3},
+  {bits: 3,  name: 'func3'},
+  {bits: 5,  name: 'rs1'},
+  {bits: 5,  name: 'rs2'},
+  {bits: 7,  name: 'imm[11:5]', type: 3}
+], config: {label: {right: 'S-Type'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 1,  name: '[11]',      type: 3},
+  {bits: 4,  name: 'imm[4:1]',  type: 3},
+  {bits: 3,  name: 'func3'},
+  {bits: 5,  name: 'rs1'},
+  {bits: 5,  name: 'rs2'},
+  {bits: 6,  name: 'imm[10:5]', type: 3},
+  {bits: 1,  name: '[12]',      type: 3}
+], config: {label: {right: 'B-Type'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'rd'},
+  {bits: 20, name: 'imm[31:12]', type: 3}
+], config: {label: {right: 'U-Type'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'rd'},
+  {bits: 8,  name: 'imm[19:12]', type: 3},
+  {bits: 1,  name: '[11]',       type: 3},
+  {bits: 10, name: 'imm[10:1]',  type: 3},
+  {bits: 1,  name: '[20]',       type: 3}
+], config: {label: {right: 'J-Type'}}}
+....
+
+
diff --git a/src/images/wavedrom/instruction_formats.adoc b/src/images/wavedrom/instruction_formats.adoc
new file mode 100644
index 0000000..60768a4
--- /dev/null
+++ b/src/images/wavedrom/instruction_formats.adoc
@@ -0,0 +1,48 @@
+//### Figure 2.2
+
+//RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done.
+
+[wavedrom, ,svg]
+----
+{reg: [
+  {bits: 7,  name: 'opcode', type: 8},
+  {bits: 5,  name: 'rd', type: 2},
+  {bits: 3,  name: 'func3', type: 8},
+  {bits: 5,  name: 'rs1', type: 4},
+  {bits: 5,  name: 'rs2', type: 4},
+  {bits: 7,  name: 'funct7', type: 8}
+], config: {label: {right: 'R-Type'}}}
+----
+
+[wavedrom, ,svg]
+----
+{reg: [
+  {bits: 7,  name: 'opcode', type: 8},
+  {bits: 5,  name: 'rd', type: 2},
+  {bits: 3,  name: 'func3', type: 8},
+  {bits: 5,  name: 'rs1', type: 4},
+  {bits: 12, name: 'imm[11:0]', type: 3},
+], config: {label: {right: 'I-Type'}}}
+----
+
+[wavedrom, ,svg]
+----
+{reg: [
+  {bits: 7,  name: 'opcode', type: 8},
+  {bits: 5,  name: 'imm[4:0]', type: 3},
+  {bits: 3,  name: 'func3', type: 8},
+  {bits: 5,  name: 'rs1', type: 4},
+  {bits: 5,  name: 'rs2', type: 4},
+  {bits: 7,  name: 'imm[11:5]', type: 3}
+], config: {label: {right: 'S-Type'}}}
+----
+
+[wavedrom, ,svg]
+----
+{reg: [
+  {bits: 7,  name: 'opcode', type: 8},
+  {bits: 5,  name: 'rd', type: 2},
+  {bits: 20,  name: 'imm[31:12]', type: 3}
+], config: {label: {right: 'U-Type'}}}
+----
+
diff --git a/src/images/wavedrom/int-comp-lui-aiupc.adoc b/src/images/wavedrom/int-comp-lui-aiupc.adoc
new file mode 100644
index 0000000..3272c53
--- /dev/null
+++ b/src/images/wavedrom/int-comp-lui-aiupc.adoc
@@ -0,0 +1,12 @@
+//FROM ## 2.4 Integer Computational Instructions
+//### Integer Register-Immediate Instructions
+//lui-aiupc-u-immed
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',     attr: ['LUI', 'AUIPC'], type: 8},
+  {bits: 5,  name: 'rd',         attr: 'dest', type: 2},
+  {bits: 20, name: 'imm[31:12]', attr: 'U-immediate[31:12]', type: 3}
+]}
+....
diff --git a/src/images/wavedrom/int-comp-slli-srli-srai.adoc b/src/images/wavedrom/int-comp-slli-srli-srai.adoc
new file mode 100644
index 0000000..338a45c
--- /dev/null
+++ b/src/images/wavedrom/int-comp-slli-srli-srai.adoc
@@ -0,0 +1,17 @@
+//FROM ## 2.4 Integer Computational Instructions
+//### Integer Register-Immediate Instructions
+//
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP-IMM', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: ['SLLI', 'SRLI', 'SRAI'], type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'src', type: 4},
+  {bits: 5,  name: 'imm[4:0]',  attr: 'shamt[4:0]', type: 3},
+  {bits: 7,  name: 'imm[11:5]', attr: [0, 0, 32], type: 8}
+]}
+....
+
+
diff --git a/src/images/wavedrom/int_reg-reg.adoc b/src/images/wavedrom/int_reg-reg.adoc
new file mode 100644
index 0000000..5531837
--- /dev/null
+++ b/src/images/wavedrom/int_reg-reg.adoc
@@ -0,0 +1,13 @@
+//### Integer Register-Register Operations
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: ['ADD', 'SLT', 'SLTU', 'AND', 'OR', 'XOR', 'SLL', 'SRL', 'SUB', 'SRA'], type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'src1', type: 4},
+  {bits: 5,  name: 'rs2',       attr: 'src2', type: 4},
+  {bits: 7,  name: 'funct7', attr: [0, 0, 0, 0, 0, 0, 0, 0, 32, 32], type: 8}
+]}
+....
diff --git a/src/images/wavedrom/integer_computational.adoc b/src/images/wavedrom/integer_computational.adoc
new file mode 100644
index 0000000..b13bffe
--- /dev/null
+++ b/src/images/wavedrom/integer_computational.adoc
@@ -0,0 +1,15 @@
+//## 2.4 Integer Computational Instructions
+//### Integer Register-Immediate Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP-IMM', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: ['ADDI', 'SLTI', 'SLTIU', 'ANDI', 'ORI', 'XORI'], type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'src', type: 4},
+  {bits: 12, name: 'imm[11:0]', attr: 'I-immediate[11:0]', type: 3}
+]}
+....
+
+//<snio>
diff --git a/src/images/wavedrom/load-reserve-st-conditional.adoc b/src/images/wavedrom/load-reserve-st-conditional.adoc
new file mode 100644
index 0000000..ae0ab62
--- /dev/null
+++ b/src/images/wavedrom/load-reserve-st-conditional.adoc
@@ -0,0 +1,19 @@
+//# 9 "A" Standard Extension for Atomic Instructions, Version 2.1
+//## 9.2 Load-Reserved/Store-Conditional Instructions
+
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'AMO', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: 'width', type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'addr', type: 4},
+  {bits: 5,  name: 'rs2',       attr: ['0', 'src'], type: 4},
+  {bits: 1,  name: 'rl', type: 8},
+  {bits: 1,  name: 'aq', type: 8},
+  {bits: 5,  name: 'funct5', attr: ['LR.W/D', 'SC.W/D'], type: 8},
+]}
+....
+
+
diff --git a/src/images/wavedrom/load_store.adoc b/src/images/wavedrom/load_store.adoc
new file mode 100644
index 0000000..9e810ec
--- /dev/null
+++ b/src/images/wavedrom/load_store.adoc
@@ -0,0 +1,23 @@
+//## 2.6 Load and Store Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'LOAD', type: 8},
+  {bits: 5,  name: 'rd', attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3', attr: 'width', type: 8},
+  {bits: 5,  name: 'rs1', attr: 'base', type: 4},
+  {bits: 12, name: 'imm[11:0]', attr: 'offset', type: 3},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',   attr: 'STORE', type: 8},
+  {bits: 5,  name: 'imm[4:0]', attr: 'offset', type: 3},
+  {bits: 3,  name: 'func3', attr: 'width', type: 8},
+  {bits: 5,  name: 'rs1', attr: 'base', type: 4},
+  {bits: 12, name: 'imm[11:0]', attr: 'offset', type: 3},
+]}
+....
diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.adoc b/src/images/wavedrom/m-st-ext-for-int-mult.adoc
new file mode 100644
index 0000000..d1255a0
--- /dev/null
+++ b/src/images/wavedrom/m-st-ext-for-int-mult.adoc
@@ -0,0 +1,28 @@
+//# 8 "M" Standard Extension for Integer Multiplication and Division, Version 2.0
+//## 8.1 Multiplication Operations
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: 'OP',            type: 8},
+  {bits: 5,  name: 'rd',     attr: 'dest',          type: 2},
+  {bits: 3,  name: 'func3',  attr: ['MUL', 'MULH', 'MULHU', 'MULHSU'], type: 8},
+  {bits: 5,  name: 'rs1',    attr: 'multiplicand',  type: 4},
+  {bits: 5,  name: 'rs2',    attr: 'multiplier',    type: 4},
+  {bits: 7,  name: 'funct7', attr: 'MULDIV',        type: 8},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: 'OP-32',         type: 8},
+  {bits: 5,  name: 'rd',     attr: 'dest',          type: 2},
+  {bits: 3,  name: 'func3',  attr: 'MULW',          type: 8},
+  {bits: 5,  name: 'rs1',    attr: 'multiplicand',  type: 4},
+  {bits: 5,  name: 'rs2',    attr: 'multiplier',    type: 4},
+  {bits: 7,  name: 'funct7', attr: 'MULDIV',        type: 8},
+]}
+....
+
+
diff --git a/src/images/wavedrom/mem_order.adoc b/src/images/wavedrom/mem_order.adoc
new file mode 100644
index 0000000..ea118f3
--- /dev/null
+++ b/src/images/wavedrom/mem_order.adoc
@@ -0,0 +1,20 @@
+//## 2.7 Memory Ordering Instructions
+
+[wavedrom.svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'MISC-MEM', type: 8},
+  {bits: 5,  name: 'rd', attr: 0},
+  {bits: 3,  name: 'func3', attr: 'FENCE', type: 8},
+  {bits: 5,  name: 'rs1', attr: 0},
+  {bits: 1,  name: 'SW', attr: 1},
+  {bits: 1,  name: 'SR', attr: 1},
+  {bits: 1,  name: 'SO', attr: 1},
+  {bits: 1,  name: 'SI', attr: 1},
+  {bits: 1,  name: 'PW', attr: 0},
+  {bits: 1,  name: 'PR', attr: 0},
+  {bits: 1,  name: 'PO', attr: 0},
+  {bits: 1,  name: 'PI', attr: 0},
+  {bits: 4,  name: 'fm', attr: 'FM', type: 8},
+]}
+....
diff --git a/src/images/wavedrom/nop-v.adoc b/src/images/wavedrom/nop-v.adoc
new file mode 100644
index 0000000..5a9941f
--- /dev/null
+++ b/src/images/wavedrom/nop-v.adoc
@@ -0,0 +1,29 @@
+//# NOP-V
+
+The RISC-V [User-Level ISA Specification](https://riscv.org/specifications/) defines NOP instruction as follows:
+
+* The NOP instruction does not change any user-visible state, except for advancing the pc.
+* NOP is encoded as \`ADDI x0, x0, 0\`.
+
+[wavedrom,svg]
+----
+{reg:[
+    {name: 'opcode', bits: 7,  attr: 0b0010011},
+    {name: 'rd',     bits: 5,  attr: 0},
+    {name: 'func3',  bits: 3,  attr: 0},
+    {name: 'rs1',    bits: 5,  attr: 0},
+    {name: 'imm',    bits: 12, attr: 0}
+], config: {hspace: width}}
+----
+
+
+NOTE: NOPs can be used to align code segments to microarchitecturally significant address boundaries, or to leave space for inline code modifications. Although **there are many possible ways** to encode a NOP, we define a canonical NOP encoding to allow microarchitectural optimizations as well as for more readable disassembly output.
+
+How many other possible ways to encode NOP?
+----
+rd = 0
+----
+
+Any Integer Computational instruction writing into \`x0\` is NOP.
+
+`
diff --git a/src/images/wavedrom/nop.adoc b/src/images/wavedrom/nop.adoc
new file mode 100644
index 0000000..b45c001
--- /dev/null
+++ b/src/images/wavedrom/nop.adoc
@@ -0,0 +1,11 @@
+//### NOP Instruction
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP-IMM', type: 8},
+  {bits: 5,  name: 'rd',        attr: 0, type: 2},
+  {bits: 3,  name: 'func3',     attr: 'ADDI', type: 8},
+  {bits: 5,  name: 'rs1',       attr: 0, type: 4},
+  {bits: 12, name: 'imm[11:0]', attr: 0, type: 3}
+]}
+....
diff --git a/src/images/wavedrom/nopv_rv32i.adoc b/src/images/wavedrom/nopv_rv32i.adoc
new file mode 100644
index 0000000..476509f
--- /dev/null
+++ b/src/images/wavedrom/nopv_rv32i.adoc
@@ -0,0 +1,62 @@
+
+//### RV32I
+
+These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (2.9)
+
+{ADDI, SLTI, SLTIU, XORI, ORI, ANDI} x0, ? ( ${ 6 * 1 << 17} )
+
+[wavedrom,svg]
+----
+{reg: [
+    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
+    {name: 'rd',     bits: 5, attr: 0},
+    {name: 'func3',  bits: 3, attr: ['ADDI', 'SLTI', 'SLTIU', 'XORI', 'ORI', 'ANDI']},
+    {bits: 17}
+], config: {hspace: width}}
+----
+
+{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
+
+[wavedrom,svg]
+----
+{reg:[
+    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
+    {name: 'rd',     bits: 5, attr: 0},
+    {name: 'func3',  bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
+    {bits: 10},
+    {name: 'imm?',   bits: 7, attr: [0, 0, 32]}
+], config: {hspace: width}}
+----
+
+{LUI, AUIPC} x0, ? ( ${ 2 * (1 << 20) } )
+
+[wavedrom,svg]
+----
+{reg:[
+    {name: 'opcode', bits: 7,  attr: ['AUIPC', 'LUI']},
+    {name: 'rd',     bits: 5,  attr: 0},
+    {bits: 20}
+], config: {hspace: width}}
+----
+
+{ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND} x0, ?, ? ( ${ 10 * 1 << 10} )
+
+[wavedrom,svg]
+----
+{reg:[
+    {name: 'OP',     bits: 7, attr: 0b0110011},
+    {name: 'rd',     bits: 5, attr: 0},
+    {name: 'func3',  bits: 3, attr: 'ADD SUB SLL SLT SLTU XOR SRL SRA OR AND'.split(' ',
+    {bits: 10},
+    {name: 'func7',  bits: 7, attr: [0, 0, 0, 0, 0, 0, 32, 32, 0, 0]}
+], config: {hspace: width}}
+----
+
+RV32I_extra = (
+  3 * 31 +
+  31 +
+  7 * 31 +
+  3 * 31 +
+  2 * 31
+)
+
diff --git a/src/images/wavedrom/rv64_lui-auipc.adoc b/src/images/wavedrom/rv64_lui-auipc.adoc
new file mode 100644
index 0000000..f03dee3
--- /dev/null
+++ b/src/images/wavedrom/rv64_lui-auipc.adoc
@@ -0,0 +1,10 @@
+//lui-auipc
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',     attr: ['LUI', 'AUIPC'], type: 8},
+  {bits: 5,  name: 'rd',         attr: 'dest', type: 2},
+  {bits: 20, name: 'imm[31:12]', attr: 'U-immediate[31:12]', type: 3}
+]}
+....
diff --git a/src/images/wavedrom/rv64i-addiw.adoc b/src/images/wavedrom/rv64i-addiw.adoc
new file mode 100644
index 0000000..5949592
--- /dev/null
+++ b/src/images/wavedrom/rv64i-addiw.adoc
@@ -0,0 +1,28 @@
+//rv64i-addiw
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP-IMM', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: ['SLLI', 'SRLI', 'SRAI'], type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'src', type: 4},
+  {bits: 6,  name: 'imm[5:0]',  attr: 'shamt[5:0]', type: 3},
+  {bits: 6,  name: 'imm[11:6]', attr: [0, 0, 32], type: 8}
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP-IMM-32', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: ['SLLIW', 'SRLIW', 'SRAIW'], type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'src', type: 4},
+  {bits: 5,  name: 'imm[4:0]',  attr: 'shamt[4:0]', type: 3},
+  {bits: 1,  name: '[5]',       attr: 0},
+  {bits: 6,  name: 'imm[11:6]', attr: [0, 0, 32], type: 8}
+]}
+....
+
+
diff --git a/src/images/wavedrom/rv64i-base-int.adoc b/src/images/wavedrom/rv64i-base-int.adoc
new file mode 100644
index 0000000..d99d98f
--- /dev/null
+++ b/src/images/wavedrom/rv64i-base-int.adoc
@@ -0,0 +1,15 @@
+//# 6 RV64I Base Integer Instruction Set, Version 2.1
+//## 6.2 Integer Computational Instructions
+//### Integer Register-Immediate Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP-IMM-32', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: 'ADDIW', type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'src', type: 4},
+  {bits: 12, name: 'imm[11:0]', attr: 'I-immediate[11:0]', type: 3}
+]}
+....
+
diff --git a/src/images/wavedrom/rv64i_int-reg-reg.adoc b/src/images/wavedrom/rv64i_int-reg-reg.adoc
new file mode 100644
index 0000000..07e528d
--- /dev/null
+++ b/src/images/wavedrom/rv64i_int-reg-reg.adoc
@@ -0,0 +1,27 @@
+
+//rv64i int-reg-reg
+//### Integer Register-Register Operations
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: ['SLL', 'SRL', 'SRA'], type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'src1', type: 4},
+  {bits: 5,  name: 'rs2',       attr: 'src2', type: 4},
+  {bits: 7,  name: 'funct7', attr: [0, 0, 32], type: 8}
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'OP-32', type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
+  {bits: 3,  name: 'func3',     attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW'], type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'src1', type: 4},
+  {bits: 5,  name: 'rs2',       attr: 'src2', type: 4},
+  {bits: 7,  name: 'funct7', attr: [0, 0, 0, 32, 32], type: 8}
+]}
+....
diff --git a/src/images/wavedrom/sp-base-ls-2.adoc b/src/images/wavedrom/sp-base-ls-2.adoc
new file mode 100644
index 0000000..5ec43c1
--- /dev/null
+++ b/src/images/wavedrom/sp-base-ls-2.adoc
@@ -0,0 +1,11 @@
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op',     type: 8, attr: 'C2'},
+  {bits: 5, name: 'rs2',    type: 4, attr: 'src'},
+  {bits: 6, name: 'imm',    type: 3, attr: ['offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]', 'offset[5:3|8:6]']},
+  {bits: 3, name: 'funct3', type: 8, attr: ['C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']},
+], config: {bits: 16}}
+....
+
diff --git a/src/images/wavedrom/sp-load-store.adoc b/src/images/wavedrom/sp-load-store.adoc
new file mode 100644
index 0000000..bc5a562
--- /dev/null
+++ b/src/images/wavedrom/sp-load-store.adoc
@@ -0,0 +1,25 @@
+//## 12.5 Single-Precision Load and Store Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'LOAD-FP',  type: 8},
+  {bits: 5,  name: 'rd',        attr: 'dest',     type: 2},
+  {bits: 3,  name: 'func3',     attr: 'width',    type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'base',     type: 4},
+  {bits: 12, name: 'imm[11:0]', attr: 'offset',   type: 3},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'STORE-FP', type: 8},
+  {bits: 5,  name: 'imm[4:0]',  attr: 'offset',   type: 3},
+  {bits: 3,  name: 'func3',     attr: 'width',    type: 8},
+  {bits: 5,  name: 'rs1',       attr: 'base',     type: 4},
+  {bits: 5,  name: 'rs2',       attr: 'src',      type: 4},
+  {bits: 12, name: 'imm[11:5]', attr: 'offset',   type: 3},
+]}
+....
+
diff --git a/src/images/wavedrom/spfloat-classify.adoc b/src/images/wavedrom/spfloat-classify.adoc
new file mode 100644
index 0000000..c46b661
--- /dev/null
+++ b/src/images/wavedrom/spfloat-classify.adoc
@@ -0,0 +1,14 @@
+//## 12.9 Single-Precision Floating-Point Classify Instruction
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: 'OP-FP',  type: 8},
+  {bits: 5, name: 'rd',     attr: 'dest',   type: 2},
+  {bits: 3, name: 'rm',     attr: 1,        type: 8},
+  {bits: 5, name: 'rs1',    attr: 'src',    type: 4},
+  {bits: 5, name: 'rs2',    attr: 0,        type: 8},
+  {bits: 2, name: 'fmt',    attr: 'S',      type: 8},
+  {bits: 5, name: 'funct5', attr: 'FCLASS', type: 8},
+]}
+....
diff --git a/src/images/wavedrom/spfloat-cn-cmp.adoc b/src/images/wavedrom/spfloat-cn-cmp.adoc
new file mode 100644
index 0000000..b19b490
--- /dev/null
+++ b/src/images/wavedrom/spfloat-cn-cmp.adoc
@@ -0,0 +1,15 @@
+//sp float convert and compare
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: 'OP-FP',    type: 8},
+  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
+  {bits: 3, name: 'func3',  attr: 'RM',       type: 8},
+  {bits: 5, name: 'rs1',    attr: 'src',      type: 4},
+  {bits: 5, name: 0,                          type: 8},
+  {bits: 2, name: 'fmt',    attr: 'S',        type: 8},
+  {bits: 5, name: 'funct5', attr: 'FSQRT',    type: 8},
+]}
+....
+
diff --git a/src/images/wavedrom/spfloat-comp.adoc b/src/images/wavedrom/spfloat-comp.adoc
new file mode 100644
index 0000000..1af7943
--- /dev/null
+++ b/src/images/wavedrom/spfloat-comp.adoc
@@ -0,0 +1,15 @@
+//## 12.8 Single-Precision Floating-Point Compare Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: 'OP-FP',  type: 8},
+  {bits: 5, name: 'rd',     attr: 'dest',   type: 2},
+  {bits: 3, name: 'func3',  attr: ['EQ', 'LT', 'LE'], type: 8},
+  {bits: 5, name: 'rs1',    attr: 'src1',   type: 4},
+  {bits: 5, name: 'rs2',    attr: 'src2',   type: 4},
+  {bits: 2, name: 'fmt',    attr: 'S',      type: 8},
+  {bits: 5, name: 'funct5', attr: 'FCMP',   type: 8},
+]}
+....
+
diff --git a/src/images/wavedrom/spfloat-mv.adoc b/src/images/wavedrom/spfloat-mv.adoc
new file mode 100644
index 0000000..625ae4d
--- /dev/null
+++ b/src/images/wavedrom/spfloat-mv.adoc
@@ -0,0 +1,15 @@
+//SP flating point move
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: 'OP-FP',    type: 8},
+  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
+  {bits: 3, name: 'func3',  attr: ['MIN', 'MAX'], type: 8},
+  {bits: 5, name: 'rs1',    attr: 'src1',     type: 4},
+  {bits: 5, name: 'rs2',    attr: 'src2',     type: 4},
+  {bits: 2, name: 'fmt',    attr: 'S',        type: 8},
+  {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8},
+]}
+....
+
diff --git a/src/images/wavedrom/spfloat.adoc b/src/images/wavedrom/spfloat.adoc
new file mode 100644
index 0000000..7b344ef
--- /dev/null
+++ b/src/images/wavedrom/spfloat.adoc
@@ -0,0 +1,17 @@
+//## 12.6 Single-Precision Floating-Point Computational Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: 'OP-FP',    type: 8},
+  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
+  {bits: 3, name: 'func3',  attr: 'RM',       type: 8},
+  {bits: 5, name: 'rs1',    attr: 'src1',     type: 4},
+  {bits: 5, name: 'rs2',    attr: 'src2',     type: 4},
+  {bits: 2, name: 'fmt',    attr: 'S',        type: 8},
+  {bits: 5, name: 'funct5', attr: ['FADD', 'FSUB', 'FMUL', 'FDIV'], type: 8},
+]}
+....
+
+
+
diff --git a/src/images/wavedrom/zifencei-fetch.adoc b/src/images/wavedrom/zifencei-fetch.adoc
new file mode 100644
index 0000000..7d473bb
--- /dev/null
+++ b/src/images/wavedrom/zifencei-fetch.adoc
@@ -0,0 +1,12 @@
+//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'MISC-MEM', type: 8},
+  {bits: 5,  name: 'rd',    attr: 0},
+  {bits: 3,  name: 'func3', attr: 'FENCE.I', type: 8},
+  {bits: 5,  name: 'rs1',   attr: 0},
+  {bits: 12, name: 'func12', attr: 0},
+]}
+....
diff --git a/src/images/wavedrom/zifencei-ff.adoc b/src/images/wavedrom/zifencei-ff.adoc
new file mode 100644
index 0000000..7d473bb
--- /dev/null
+++ b/src/images/wavedrom/zifencei-ff.adoc
@@ -0,0 +1,12 @@
+//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'MISC-MEM', type: 8},
+  {bits: 5,  name: 'rd',    attr: 0},
+  {bits: 3,  name: 'func3', attr: 'FENCE.I', type: 8},
+  {bits: 5,  name: 'rs1',   attr: 0},
+  {bits: 12, name: 'func12', attr: 0},
+]}
+....
diff --git a/src/images/wavedrom/zihintpause-hint.adoc b/src/images/wavedrom/zihintpause-hint.adoc
new file mode 100644
index 0000000..86d966a
--- /dev/null
+++ b/src/images/wavedrom/zihintpause-hint.adoc
@@ -0,0 +1,21 @@
+//# 4 "Zihintpause" Pause Hint, Version 1.0
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'MISC-MEM', type: 8},
+  {bits: 5,  name: 'rd', attr: 0},
+  {bits: 3,  name: 'func3', attr: 'PAUSE', type: 8},
+  {bits: 5,  name: 'rs1', attr: 0},
+  {bits: 1,  name: 'SW', attr: 1},
+  {bits: 1,  name: 'SR', attr: 0},
+  {bits: 1,  name: 'SO', attr: 0},
+  {bits: 1,  name: 'SI', attr: 0},
+  {bits: 1,  name: 'PW', attr: 0},
+  {bits: 1,  name: 'PR', attr: 0},
+  {bits: 1,  name: 'PO', attr: 0},
+  {bits: 1,  name: 'PI', attr: 0},
+  {bits: 4,  name: 'fm', attr: 0},
+]}
+....
+