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| author | allen1130 <yiteng891130@gmail.com> | 2023-10-16 22:24:12 +0800 |
|---|---|---|
| committer | allen1130 <yiteng891130@gmail.com> | 2023-10-16 22:24:12 +0800 |
| commit | e9060f404e923db28618e257b2de18a0d4087429 (patch) | |
| tree | 43b5293bb7d8c49d31a631b88006772f4ead1dff /src/images/wavedrom | |
| parent | 5d4f86ba24ef939f371b52ab40f073ab0fde2988 (diff) | |
| download | riscv-isa-manual-e9060f404e923db28618e257b2de18a0d4087429.zip riscv-isa-manual-e9060f404e923db28618e257b2de18a0d4087429.tar.gz riscv-isa-manual-e9060f404e923db28618e257b2de18a0d4087429.tar.bz2 | |
Fix wrong bit length of rd field
The bit length of rd register should be 5 instead of 3.
Diffstat (limited to 'src/images/wavedrom')
| -rw-r--r-- | src/images/wavedrom/csr-instr.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.adoc index e4a54a5..93022be 100644 --- a/src/images/wavedrom/csr-instr.adoc +++ b/src/images/wavedrom/csr-instr.adoc @@ -5,7 +5,7 @@ .... {reg: [ {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['3', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2}, {bits: 3, name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8}, {bits: 5, name: 'rs1', attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'], type: 4}, {bits: 12, name: 'csr', attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], type: 4}, |