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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-05-03 17:59:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-05-03 17:59:22 -0700 |
| commit | be663aebca2f8dd9572bf7071e2d721db729c1ba (patch) | |
| tree | 132a0de50730d3be8d190219fb1451ca07c0b0e7 /src/hypervisor.tex | |
| parent | 197e88ea34371320ca4b5d6a85f4cba972d81635 (diff) | |
| download | riscv-isa-manual-be663aebca2f8dd9572bf7071e2d721db729c1ba.zip riscv-isa-manual-be663aebca2f8dd9572bf7071e2d721db729c1ba.tar.gz riscv-isa-manual-be663aebca2f8dd9572bf7071e2d721db729c1ba.tar.bz2 | |
Fix typo confusing TVM and TSR. (#170)
Diffstat (limited to 'src/hypervisor.tex')
| -rw-r--r-- | src/hypervisor.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 30fd913..63dfc65 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -905,9 +905,9 @@ address, and the ASID argument is an S-level ASID. The instruction orders stores only to the S-level address-translation structures within the HS-level address-space specified by the {\tt bsatp} register. -When V=0, attempts to execute SFENCE.VMA in U-mode or when {\tt mstatus}.TSR=1 +When V=0, attempts to execute SFENCE.VMA in U-mode or when {\tt mstatus}.TVM=1 raise an illegal instruction exception. When V=1, attempts to execute -SFENCE.VMA in U-mode or when {\tt hstatus}.VTSR=1 raise an illegal instruction +SFENCE.VMA in U-mode or when {\tt hstatus}.VTVM=1 raise an illegal instruction exception. \subsection{Trap Value Register Discipline} |