From be663aebca2f8dd9572bf7071e2d721db729c1ba Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur <prashanth.mundkur@gmail.com>
Date: Thu, 3 May 2018 17:59:22 -0700
Subject: Fix typo confusing TVM and TSR. (#170)

---
 src/hypervisor.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/hypervisor.tex')

diff --git a/src/hypervisor.tex b/src/hypervisor.tex
index 30fd913..63dfc65 100644
--- a/src/hypervisor.tex
+++ b/src/hypervisor.tex
@@ -905,9 +905,9 @@ address, and the ASID argument is an S-level ASID.  The instruction
 orders stores only to the S-level address-translation structures within the
 HS-level address-space specified by the {\tt bsatp} register.
 
-When V=0, attempts to execute SFENCE.VMA in U-mode or when {\tt mstatus}.TSR=1
+When V=0, attempts to execute SFENCE.VMA in U-mode or when {\tt mstatus}.TVM=1
 raise an illegal instruction exception.  When V=1, attempts to execute
-SFENCE.VMA in U-mode or when {\tt hstatus}.VTSR=1 raise an illegal instruction
+SFENCE.VMA in U-mode or when {\tt hstatus}.VTVM=1 raise an illegal instruction
 exception.
 
 \subsection{Trap Value Register Discipline}
-- 
cgit v1.1

