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| author | Bill Traynor <wmat@riscv.org> | 2023-04-18 10:16:22 -0400 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-04-18 10:16:22 -0400 |
| commit | 6e5d2202b372fa268ba4866afdb36ef24bbe5181 (patch) | |
| tree | 887dce13452cc937703cac09b225df1444926de6 /src/hypervisor.adoc | |
| parent | 1b0a1a92f7f2990ab5c3fff85657bcf303413c14 (diff) | |
| download | riscv-isa-manual-6e5d2202b372fa268ba4866afdb36ef24bbe5181.zip riscv-isa-manual-6e5d2202b372fa268ba4866afdb36ef24bbe5181.tar.gz riscv-isa-manual-6e5d2202b372fa268ba4866afdb36ef24bbe5181.tar.bz2 | |
Cleaning up conversion issues
Cleaning up characters that didn't convert
correctly
Diffstat (limited to 'src/hypervisor.adoc')
| -rw-r--r-- | src/hypervisor.adoc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 9e4556c..e4db97c 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -1696,17 +1696,17 @@ Specifically, a virtual instruction exception is raised for the following cases: * in VS-mode, attempts to access a non-high-half counter CSR when the -corresponding bit in `hcounteren` is 0 and the same bit in `mcounteren` -is 1; +corresponding bit in `hcounteren` is 0 and the same bit in `mcounteren` +is 1; * in VS-mode, if XLEN=32, attempts to access a high-half counter CSR -when the corresponding bit in `hcounteren` is 0 and the same bit in -`mcounteren` is 1; +when the corresponding bit in `hcounteren` is 0 and the same bit in +`mcounteren` is 1; * in VU-mode, attempts to access a non-high-half counter CSR when the -corresponding bit in either `hcounteren` or `scounteren` is 0 and the -same bit in `mcounteren` is 1; +corresponding bit in either `hcounteren` or `scounteren` is 0 and the +same bit in `mcounteren` is 1; * in VU-mode, if XLEN=32, attempts to access a high-half counter CSR -when the corresponding bit in either `hcounteren` or `scounteren` is 0 -and the same bit in `mcounteren` is 1; +when the corresponding bit in either `hcounteren` or `scounteren` is 0 +and the same bit in `mcounteren` is 1; * in VS-mode or VU-mode, attempts to execute a hypervisor instruction (HLV, HLVX, HSV, or HFENCE); * in VS-mode or VU-mode, attempts to access an implemented non-high-half @@ -1714,7 +1714,7 @@ hypervisor CSR or VS CSR when the same access (read/write) would be allowed in HS-mode, assuming `mstatus`.TVM=0; * in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented high-half hypervisor CSR or high-half VS CSR when the same access -(read/write) to the CSR’s low-half partner would be allowed in HS-mode, +(read/write) to the CSR"s low-half partner would be allowed in HS-mode, assuming `mstatus`.TVM=0; * in VU-mode, attempts to execute WFI when `mstatus`.TW=0, or to execute a supervisor instruction (SRET or SFENCE); @@ -1722,7 +1722,7 @@ a supervisor instruction (SRET or SFENCE); CSR when the same access (read/write) would be allowed in HS-mode, assuming `mstatus`.TVM=0; * in VU-mode, if XLEN=32, attempts to access an implemented high-half -supervisor CSR when the same access to the CSR’s low-half partner would +supervisor CSR when the same access to the CSR's low-half partner would be allowed in HS-mode, assuming `mstatus`.TVM=0; * in VS-mode, attempts to execute WFI when `hstatus`.VTW=1 and `mstatus`.TW=0, unless the instruction completes within an |