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| author | Andrew Waterman <andrew@sifive.com> | 2018-04-28 16:03:11 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-04-28 16:03:11 -0700 |
| commit | de8d4a5b0d0957347f6ec88d02e8fe778b44f9f5 (patch) | |
| tree | ea2ad399409087215167b7128c1e68d92f75e217 /src/f.tex | |
| parent | 1400e614a790fc4b9ef0f89b69acaeab8a7d0207 (diff) | |
| download | riscv-isa-manual-de8d4a5b0d0957347f6ec88d02e8fe778b44f9f5.zip riscv-isa-manual-de8d4a5b0d0957347f6ec88d02e8fe778b44f9f5.tar.gz riscv-isa-manual-de8d4a5b0d0957347f6ec88d02e8fe778b44f9f5.tar.bz2 | |
Add paragraph break
Diffstat (limited to 'src/f.tex')
| -rw-r--r-- | src/f.tex | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -611,7 +611,9 @@ single-precision value in floating-point register {\em rs1} represented in IEEE 754-2008 encoding to the lower 32 bits of integer register {\em rd}. For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number's sign -bit. FMV.W.X moves the single-precision value encoded in IEEE +bit. + +FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register {\em rs1} to the floating-point register {\em rd}. The bits are not modified in the transfer, and in particular, the payloads of |