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| author | elisa <elisa@riscv.org> | 2021-10-22 11:25:16 -0700 |
|---|---|---|
| committer | elisa <elisa@riscv.org> | 2021-10-22 11:25:16 -0700 |
| commit | f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d (patch) | |
| tree | 0ce6ae0478d3ad3b20f42131a7e80788c9876e41 /src/f-st-ext.adoc | |
| parent | a4954af2fd406e6f7fb9a1925d5b870c6bb155ec (diff) | |
| download | riscv-isa-manual-f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d.zip riscv-isa-manual-f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d.tar.gz riscv-isa-manual-f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d.tar.bz2 | |
table and diagram fixes, added some missing c diagrams
Diffstat (limited to 'src/f-st-ext.adoc')
| -rw-r--r-- | src/f-st-ext.adoc | 43 |
1 files changed, 41 insertions, 2 deletions
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc index 7151f2a..1bd2f9a 100644 --- a/src/f-st-ext.adoc +++ b/src/f-st-ext.adoc @@ -36,8 +36,47 @@ floating-point register file state can reduce context-switch overhead. ==== [[fprs]] -.RISC-V standard F extension single-precision floating-point state -image::f-standard.png[base,180,1000,align="center"] +.RISC-V standard F exten[sion single-precision floating-point state +[col[s="<|^|>"|option[s="header",width="50%",align="center"grid="none"] +|=== +<| [small]#FLEN-1#| >| [small]#0# +3+^| [small]#f0# +3+^| [small]#f1# +3+^| [small]#f2# +3+^| [small]#f3# +3+^| [small]#f4# +3+^| [small]#f5# +3+^| [small]#f6# +3+^| [small]#f7# +3+^| [small]#f8# +3+^| [small]#f9# +3+^| [small]#f10# +3+^| [small]#f11# +3+^| [small]#f12# +3+^| [small]#f13# +3+^| [small]#f14# +3+^| [small]#f15# +3+^| [small]#f16# +3+^| [small]#f17# +3+^| [small]#f18# +3+^| [small]#f19# +3+^| [small]#f20# +3+^| [small]#f21# +3+^| [small]#f22# +3+^| [small]#f23# +3+^| [small]#f24# +3+^| [small]#f25# +3+^| [small]#f26# +3+^| [small]#f27# +3+^| [small]#f28# +3+^| [small]#f29# +3+^| [small]#f30# +3+^| [small]#f31# +3+^| [small]#FLEN# +| [small]#31#| >| [small]#0# +3+^| [small]#fcsr# +3+^| [small]#32# +|=== === Floating-Point Control and Status Register |