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author | Vedvyas Shanbhogue <ved@rivosinc.com> | 2021-10-11 17:16:46 -0500 |
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committer | Vedvyas Shanbhogue <ved@rivosinc.com> | 2021-10-11 17:16:46 -0500 |
commit | 7b8d6fb027f140d96504e55b9a0d6d9942a59543 (patch) | |
tree | 102849257ca47dfc981d3f892be01827fa5d50ab /src/f-st-ext.adoc | |
parent | ce5c5e046d1dead21e61fe6dce309f83222cf7b6 (diff) | |
download | riscv-isa-manual-7b8d6fb027f140d96504e55b9a0d6d9942a59543.zip riscv-isa-manual-7b8d6fb027f140d96504e55b9a0d6d9942a59543.tar.gz riscv-isa-manual-7b8d6fb027f140d96504e55b9a0d6d9942a59543.tar.bz2 |
f-st-ext.adoc
~~~~~~~~~~~~~
1. removed extra white space ahead of a fcsr instance
2. Removed extra row in Table 7
3. Corrected cross reference to point to Ld/St section chapter 2
4. Fixed wrong wavedrom file included in section 12.7
float-csr.adoc
~~~~~~~~~~~~~~
Add the labels back for fflags and frm
sp-load-store.adoc
~~~~~~~~~~~~~~~~~~
1. Fixed bitfield name that encodes width to denote width and not func3
2. Added bit range to offset.
spfloat-classify.adoc
~~~~~~~~~~~~~~~~~~~~~
1. Fixed attribute to be quoted to avoid repeating
spfloat-cn-cmp.adoc
~~~~~~~~~~~~~~~~~~~
1. Deleted wrongly include FSQRT and replaced with FCVT.int.fmt and FCVT.fmt.int
2. Added missing FSGNJ
spfloat-comp.doc
~~~~~~~~~~~~~~~~
1. Corrected bit field name func3 to rm
spfloat-mv.adoc
~~~~~~~~~~~~~~~
1. Deleted incorrect FMIN-FMAX
2. Added missing FMV.X.W and FMV.W.X
spfloat.adoc
1. Corrected the attributes
2. Added missing FSQRT and FMIN-MAX
Diffstat (limited to 'src/f-st-ext.adoc')
-rw-r--r-- | src/f-st-ext.adoc | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc index 7b3d0e9..7151f2a 100644 --- a/src/f-st-ext.adoc +++ b/src/f-st-ext.adoc @@ -54,7 +54,7 @@ image::image_placeholder.png[] The `fcsr` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads `fcsr` by copying it -into integer register _rd_. FSCSR swaps the value in ` fcsr` by copying +into integer register _rd_. FSCSR swaps the value in `fcsr` by copying the original value into integer register _rd_, and then writing a new value obtained from integer register _rs1_ into `fcsr`. @@ -98,8 +98,7 @@ particular, with regard to decoding legal vs. reserved encodings). |100 |RMM |Round to Nearest, ties to Max Magnitude |101 | |_Reserved for future use._ |110 | |_Reserved for future use._ -|111 |DYN |In instruction’s _rm_ field, selects dynamic rounding mode; -| | |In Rounding Mode register, _reserved_. +|111 |DYN |In instruction’s _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_. |=== [NOTE] @@ -218,7 +217,7 @@ address is naturally aligned. FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. -As described in <<sp-ldst>>, the execution +As described in <<ldst>>, the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap. @@ -390,7 +389,7 @@ All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. -include::images/wavedrom/spfloat.adoc[] +include::images/wavedrom/spfloat-cn-cmp.adoc[] [[fcvt]] .SP float convert and move image::image_placeholder.png[] @@ -408,11 +407,6 @@ pseudoinstruction FNEG.S _rx, ry_); and FSGNJX.S _rx, ry, ry_ moves the absolute value of _ry_ to _rx_ (assembler pseudoinstruction FABS.S _rx, ry_). -include::images/wavedrom/spfloat-cn-cmp.adoc[] -[[spfloat-cn-cmp]] -.SP floating point convert and compare -image::image_placeholder.png[] - [NOTE] ==== The sign-injection instructions provide floating-point MV, ABS, and NEG, |