Add ILEN to simplify descriptions of {m,s}tval CSRs

1 files changed, 9 insertions, 0 deletions

diff --git a/src/extensions.tex b/src/extensions.tex
index 4346422..efd0760 100644
--- a/src/extensions.tex
+++ b/src/extensions.tex
@@ -52,6 +52,15 @@ example, the base ISA is defined within a 30-bit encoding space (bits
 31--2 of the 32-bit instruction), while the atomic extension ``A''
 fits within a 25-bit encoding space (bits 31--7).
 
+We use the term ILEN to refer to the maximum instruction length supported
+by an implementation, which is always a multiple of 16 bits.  For
+implementations supporting only the base instruction set, ILEN is 32 bits.
+Implementations supporting longer instructions have larger values of ILEN.
+ILEN is implied from the set of extensions implemented, or can be
+explicitly defined in the platform configuration if an implementation is
+designed to support an extension that uses longer instructions via software
+emulation but does not actually decode longer instructions in hardware.
+
 We use the term {\em prefix} to refer to the bits to the {\em right}
 of an instruction encoding space (since RISC-V is little-endian, the
 bits to the right are stored at earlier memory addresses, hence form a