Some formatting and admonition adds.

Added missing admonitions.
Formatting of monospaced fonts.

1 files changed, 15 insertions, 13 deletions

diff --git a/src/extending.adoc b/src/extending.adoc
index 965f1f3..4ea00c0 100644
--- a/src/extending.adoc
+++ b/src/extending.adoc
@@ -64,11 +64,11 @@ instruction spaces.
 Although an instruction encoding space could be of any size, adopting a
 smaller set of common sizes simplifies packing independently developed
 extensions into a single global encoding.
-<<encodingspaces, Table 40>> gives the suggested sizes for RISC-V.
+<<encodingspaces>> gives the suggested sizes for RISC-V.
 
 [[encodingspaces]]
 .Suggested standard RISC-V instruction encoding space sizes.
-[cols="^2,<12,>3,>3,>3,>3"]
+[%autowidth,float="center",align="center",cols="^,<,>,>,>,>", options="header"]
 |===
 |Size |Usage 
 4+^| # Available in standard instruction length
@@ -128,15 +128,15 @@ itself.
 
 [[exttax]]
 .Two-dimensional characterization of standard instruction-set extensions.
-[cols=">,^,^",options="header",]
-[%autowidth, align=center]
+[cols="^,^,^",options="header",]
+[%autowidth, float="center", align="center"]
 |===
 |           |Adds state           |No new state
 |Greenfield |RV32I(30), RV64I(30) |A(25)
 |Brownfield |F(I), D(F), Q(D)     |M(I)
 |===
 
-<<exttax, Table 41>> shows the bases and standard extensions placed
+<<exttax>> shows the bases and standard extensions placed
 in a simple two-dimensional taxonomy. One axis is whether the extension
 is greenfield or brownfield, while the other axis is whether the
 extension adds architectural state. For greenfield extensions, the size
@@ -224,14 +224,15 @@ development.
 
 In this section, we discuss adding extensions to implementations that
 only support the base fixed-width 32-bit instruction format.
-
+[NOTE]
+====
 We anticipate the simplest fixed-width 32-bit encoding will be popular
 for many restricted accelerators and research prototypes.
-
+====
 ==== Available 30-bit instruction encoding spaces
 
 In the standard encoding, three of the available 30-bit instruction
-encoding spaces (those with 2-bit prefixes 00, 01, and 10) are used to
+encoding spaces (those with 2-bit prefixes `00`, `01`, and `10`) are used to
 enable the optional compressed instruction extension. However, if the
 compressed instruction-set extension is not required, then these three
 further 30-bit encoding spaces become available. This quadruples the
@@ -243,7 +244,7 @@ A 25-bit instruction encoding space corresponds to a major opcode in the
 base and standard extension encodings.
 
 There are four major opcodes expressly designated for custom extensions
-<<opcodemap, Table 38>>, each of which represents a 25-bit
+<<opcodemap>>, each of which represents a 25-bit
 encoding space. Two of these are reserved for eventual use in the RV128
 base encoding (will be OP-IMM-64 and OP-64), but can be used for
 non-standard extensions for RV32 and RV64.
@@ -259,7 +260,7 @@ if the standard atomic extensions are not required.
 
 If an implementation does not require instructions longer than 32-bits,
 then an additional four major opcodes are available (those marked in
-gray in <<opcodemap, Table 38>>.
+gray in <<opcodemap>>).
 
 The base RV32I encoding uses only 11 major opcodes plus 3 reserved
 opcodes, leaving up to 18 available for extensions. The base RV64I
@@ -300,11 +301,12 @@ standard encoding for 32-bit instructions. For example, if compressed
 instructions are not required, then a 64-bit instruction could be
 encoded using one or more zero bits in the first two bits of an
 instruction.
-
+[NOTE]
+====
 We anticipate processor generators that produce instruction-fetch units
 capable of automatically handling any combination of supported
 variable-length instruction encodings.
-
+====
 === Supporting VLIW encodings
 
 Although RISC-V was not designed as a base for a pure VLIW machine, VLIW
@@ -324,7 +326,7 @@ VLIW code size expansion to VLIW-accelerated functions.
 ==== Encoded-Length Groups
 
 Another approach is to use the standard length encoding from
-<<instlengthcode, Table 1>> to encode parallel
+<<instlengthcode>> to encode parallel
 instruction groups, allowing NOPs to be compressed out of the VLIW
 instruction. For example, a 64-bit instruction could hold two 28-bit
 operations, while a 96-bit instruction could hold three 28-bit