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author | Andrew Waterman <andrew@sifive.com> | 2019-12-05 12:21:03 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-12-05 12:21:51 -0800 |
commit | 80e635f25e407cd469edf7412adaa493462debf6 (patch) | |
tree | 3bc60d1e5c1f7d3eebdcb0f8c7d746851c005263 /src/dep-table.tex | |
parent | 45e063b17f98b980efe9dd8a75a49680adbb040d (diff) | |
download | riscv-isa-manual-80e635f25e407cd469edf7412adaa493462debf6.zip riscv-isa-manual-80e635f25e407cd469edf7412adaa493462debf6.tar.gz riscv-isa-manual-80e635f25e407cd469edf7412adaa493462debf6.tar.bz2 |
Forgot to include frm as PPO source for FCVT.L[U].S/FCVT.S.L[U]
Diffstat (limited to 'src/dep-table.tex')
-rw-r--r-- | src/dep-table.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/dep-table.tex b/src/dep-table.tex index c84cecd..a54ed03 100644 --- a/src/dep-table.tex +++ b/src/dep-table.tex @@ -365,13 +365,13 @@ $^\ddagger$The instruction carries dependencies from source register(s) to desti & Source & Destination & Accumulating \\ & Registers & Registers & CSRs \\ \cline{2-4} - FCVT.L.S & {\em rs1} & {\em rd} & NV, NX & \\ + FCVT.L.S & {\em rs1}, frm$^*$ & {\em rd} & NV, NX & $^*$if rm=111 \\ \cline{2-4} - FCVT.LU.S & {\em rs1} & {\em rd} & NV, NX & \\ + FCVT.LU.S & {\em rs1}, frm$^*$ & {\em rd} & NV, NX & $^*$if rm=111 \\ \cline{2-4} - FCVT.S.L & {\em rs1} & {\em rd} & NX & \\ + FCVT.S.L & {\em rs1}, frm$^*$ & {\em rd} & NX & $^*$if rm=111 \\ \cline{2-4} - FCVT.S.LU & {\em rs1} & {\em rd} & NX & \\ + FCVT.S.LU & {\em rs1}, frm$^*$ & {\em rd} & NX & $^*$if rm=111 \\ \cline{2-4} \end{tabular} |