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authorBill Traynor <wmat@riscv.org>2022-12-06 16:56:06 -0500
committerBill Traynor <wmat@riscv.org>2022-12-06 16:56:06 -0500
commitefe172ca70b0c1ad39b5a9df6a1d998074e80796 (patch)
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parent035669fb97770d238b38401ce023697d87695197 (diff)
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Commented out figure labels
Commented out figure labels and deleted image placeholders.
Diffstat (limited to 'src/d-st-ext.adoc')
-rw-r--r--src/d-st-ext.adoc64
1 files changed, 23 insertions, 41 deletions
diff --git a/src/d-st-ext.adoc b/src/d-st-ext.adoc
index 8b4885c..baf931a 100644
--- a/src/d-st-ext.adoc
+++ b/src/d-st-ext.adoc
@@ -10,8 +10,8 @@ the base single-precision instruction subset F.
=== D Register State
-The D extension widens the 32 floating-point registers, `f0–f31`, to
-64 bits (FLEN=64 in <<fprs-d>>. The `f` registers can
+The D extension widens the 32 floating-point registers, 'f0-f31', to
+64 bits (FLEN=64 in <<fprs-d>>. The 'f' registers can
now hold either 32-bit or 64-bit floating-point values as described
below in <<nanboxing>>.
@@ -27,15 +27,9 @@ floating-point precisions supported, including H, F, D, and Q.
=== NaN Boxing of Narrower Values
When multiple floating-point precisions are supported, then valid values
-of narrower latexmath:[$n$]-bit types, latexmath:[$n<$]FLEN, are
-represented in the lower latexmath:[$n$] bits of an FLEN-bit NaN value,
-in a process termed NaN-boxing. The upper bits of a valid NaN-boxed
-value must be all 1s. Valid NaN-boxed latexmath:[$n$]-bit values
+of narrower _n_-bit types, _n<_FLEN, are represented in the lower _n_ bits of an FLEN-bit NaN value, in a process termed NaN-boxing. The upper bits of a valid NaN-boxed value must be all 1s. Valid NaN-boxed _n_-bit values
therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider
-latexmath:[$m$]-bit value, latexmath:[$n < m \leq$]FLEN. Any operation
-that writes a narrower result to an `f` register must write all 1s to
-the uppermost FLENlatexmath:[$-n$] bits to yield a legal NaN-boxed
-value.
+_m_-bit value, _n_ < _m_ &#8804; FLEN. Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost FLEN-_n_ bits to yield a legal NaN-boxedvalue.
(((floating-point, requirements)))
[NOTE]
@@ -49,24 +43,20 @@ including varargs, user-level threading libraries, virtual machine
migration, and debugging.
====
-Floating-point latexmath:[$n$]-bit transfer operations move external
-values held in IEEE standard formats into and out of the `f` registers,
-and comprise floating-point loads and stores
-(FLlatexmath:[$n$]/FSlatexmath:[$n$]) and floating-point move
-instructions (FMV.latexmath:[$n$].X/FMV.X.latexmath:[$n$]). A narrower
-latexmath:[$n$]-bit transfer, latexmath:[$n<$]FLEN, into the `f`
-registers will create a valid NaN-boxed value. A narrower
-latexmath:[$n$]-bit transfer out of the floating-point registers will
-transfer the lower latexmath:[$n$] bits of the register ignoring the
-upper FLENlatexmath:[$-n$] bits.
+Floating-point _n_-bit transfer operations move external
+values held in IEEE standard formats into and out of the 'f' registers,
+and comprise floating-point loads and stores (FL_n_/FS_n_) and floating-point move instructions (FMV._n_.X/FMV.X._n_). A narrower _n_-bit transfer, _n_<FLEN, into the 'f' registers will create a valid NaN-boxed value. A narrower
+_n_-bit transfer out of the floating-point registers will
+transfer the lower _n_ bits of the register ignoring the
+upper FLEN-_n_ bits.
Apart from transfer operations described in the previous paragraph, all
other floating-point operations on narrower latexmath:[$n$]-bit
-operations, latexmath:[$n<$]FLEN, check if the input operands are
-correctly NaN-boxed, i.e., all upper FLENlatexmath:[$-n$] bits are 1. If
-so, the latexmath:[$n$] least-significant bits of the input are used as
+operations, _n_<FLEN, check if the input operands are
+correctly NaN-boxed, i.e., all upper FLEN-_n_ bits are 1. If
+so, the _n_ least-significant bits of the input are used as
the input value, otherwise the input value is treated as an
-latexmath:[$n$]-bit canonical NaN.
+_n_-bit canonical NaN.
[TIP]
====
@@ -106,7 +96,7 @@ skipping over leading-0 bits, allowing the datapath muxing to be shared.
The FLD instruction loads a double-precision floating-point value from
memory into floating-point register _rd_. FSD stores a double-precision
value from the floating-point registers to memory.
-((floating point, load and store))
+(((floating point, load and store)))
[NOTE]
====
@@ -115,8 +105,7 @@ The double-precision value may be a NaN-boxed single-precision value.
include::images/wavedrom/double-ls.adoc[]
[[double-ls]]
-.Double-precision load and store
-image::image_placeholder.png[]
+//.Double-precision load and store
FLD and FSD are only guaranteed to execute atomically if the effective
address is naturally aligned and XLENlatexmath:[$\geq$]64.
@@ -132,8 +121,7 @@ on double-precision operands and produce double-precision results.
include::images/wavedrom/double-fl-compute.adoc[]
[[fl-compute]]
-.Double-precision float computational
-image::image_placeholder.png[]
+//.Double-precision float computational
=== Double-Precision Floating-Point Conversion and Move Instructions
@@ -157,8 +145,7 @@ produces an exact result and is unaffected by rounding mode.
include::images/wavedrom/double-fl-convert-mv.adoc[]
[[fl-convert-mv]]
-.Double-precision float convert and move
-image::image_placeholder.png[]
+//.Double-precision float convert and move
The double-precision to single-precision and single-precision to
double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are
@@ -172,8 +159,7 @@ never round.
include::images/wavedrom/fcvt-sd-ds.adoc[]
[[fcvt-sd-ds]]
-.Double-precision FCVT.S.D and FCVT.D.S
-image::image_placeholder.png[]
+//.Double-precision FCVT.S.D and FCVT.D.S
Floating-point to floating-point sign-injection instructions, FSGNJ.D,
FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision
@@ -181,8 +167,7 @@ sign-injection instruction.
//FSGNJ.D, FSGNJN.D, and FSGNJX.D
include::images/wavedrom/fsjgnjnx-d.adoc[]
-.Double-precision sign-injection
-image::image_placeholder.png[]
+//.Double-precision sign-injection
For XLENlatexmath:[$\geq$]64 only, instructions are provided to move bit
patterns between the floating-point and integer registers. FMV.X.D moves
@@ -197,8 +182,7 @@ particular, the payloads of non-canonical NaNs are preserved.
include::images/wavedrom/d-xwwx.adoc[]
[[fmvxddx]]
-.Double-precision float move to _rd_
-image::image_placeholder.png[]
+//.Double-precision float move to _rd_
[TIP]
====
@@ -232,8 +216,7 @@ double-precision operands.
include::images/wavedrom/double-fl-compare.adoc[]
[[fl-compare]]
-.Double-precision float compare
-image::image_placeholder.png[]
+//.Double-precision float compare
=== Double-Precision Floating-Point Classify Instruction
@@ -244,7 +227,6 @@ double-precision operands.
include::images/wavedrom/double-fl-class.adoc[]
[[fl-class]]
-.Double-precision float classify
-image::image_placeholder.png[]
+//.Double-precision float classify