Added backticks for monospaced formatting.

Added back in the backticks necessary for monospaced
formatting.

1 files changed, 41 insertions, 41 deletions

diff --git a/src/colophon.adoc b/src/colophon.adoc
index 0d1afb0..0106820 100644
--- a/src/colophon.adoc
+++ b/src/colophon.adoc
@@ -194,11 +194,11 @@ their semantics, has been defined.
 * The "Ztso" extension, which enforces a stricter memory consistency
 model than RVWMO, has been defined.
 * Improvements to the description and commentary.
-* Defined the term IALIGN as shorthand to describe the
+* Defined the term `IALIGN` as shorthand to describe the
 instruction-address alignment constraint.
-* Removed text of P extension chapter as now superseded by active task
+* Removed text of `P` extension chapter as now superseded by active task
 group documents.
-* Removed text of V extension chapter as now superseded by separate
+* Removed text of `V` extension chapter as now superseded by separate
 vector extension draft document.
 
 *_Preface to Document Version 2.2_*
@@ -243,21 +243,21 @@ and this and future versions of this document will be released under the
 same license.
 * Rearranged chapters to put all extensions first in canonical order.
 * Improvements to the description and commentary.
-* Modified implicit hinting suggestion on JALR to support more efficient
-macro-op fusion of LUI/JALR and AUIPC/JALR pairs.
+* Modified implicit hinting suggestion on `JALR` to support more efficient
+macro-op fusion of `LUI/JALR` and `AUIPC/JALR` pairs.
 * Clarification of constraints on load-reserved/store-conditional
 sequences.
 * A new table of control and status register (CSR) mappings.
-* Clarified purpose and behavior of high-order bits of *fcsr*.
-* Corrected the description of the FNMADD._fmt_ and FNMSUB._fmt_
+* Clarified purpose and behavior of high-order bits of `fcsr`.
+* Corrected the description of the `FNMADD`._fmt_ and `FNMSUB`._fmt_
 instructions, which had suggested the incorrect sign of a zero result.
-* Instructions FMV.S.X and FMV.X.S were renamed to FMV.W.X and FMV.X.W
+* Instructions `FMV.S.X` and `FMV.X.S` were renamed to `FMV.W.X` and `FMV.X.W`
 respectively to be more consistent with their semantics, which did not
 change. The old names will continue to be supported in the tools.
 * Specified behavior of narrower (latexmath:[$<$]FLEN) floating-point
 values held in wider `f` registers using NaN-boxing model.
 * Defined the exception behavior of FMA(latexmath:[$\infty$], 0, qNaN).
-* Added note indicating that the P extension might be reworked into an
+* Added note indicating that the `P` extension might be reworked into an
 integer packed-SIMD proposal for fixed-point operations using the
 integer registers.
 * A draft proposal of the V vector instruction-set extension.
@@ -270,7 +270,7 @@ by the RISC-V ELF psABI Specification cite:[riscv-elf-psabi].
 *_Preface to Document Version 2.1_*
 
 This is version 2.1 of the document describing the RISC-V user-level
-architecture. Note the frozen user-level ISA base and extensions IMAFDQ
+architecture. Note the frozen user-level ISA base and extensions `IMAFDQ`
 version 2.0 have not changed from the previous version of this
 document cite:[riscvtr2], but some specification holes have been fixed and the
 documentation has been improved. Some changes have been made to the
@@ -284,20 +284,20 @@ avoid moving the _rd_ specifier in very long instruction formats.
 the counter registers are introduced, as opposed to only being
 introduced later in the floating-point section (and the companion
 privileged architecture manual).
-* The SCALL and SBREAK instructions have been renamed to ECALL and
-EBREAK, respectively. Their encoding and functionality are unchanged.
+* The SCALL and SBREAK instructions have been renamed to `ECALL` and
+`EBREAK`, respectively. Their encoding and functionality are unchanged.
 * Clarification of floating-point NaN handling, and a new canonical NaN
 value.
 * Clarification of values returned by floating-point to integer
 conversions that overflow.
-* Clarification of LR/SC allowed successes and required failures,
+* Clarification of `LR/SC` allowed successes and required failures,
 including use of compressed instructions in the sequence.
-* A new RV32E base ISA proposal for reduced integer register counts,
-supports MAC extensions.
+* A new `RV32E` base ISA proposal for reduced integer register counts,
+supports `MAC` extensions.
 * A revised calling convention.
 * Relaxed stack alignment for soft-float calling convention, and
 description of the RV32E calling convention.
-* A revised proposal for the C compressed extension, version 1.9 .
+* A revised proposal for the `C` compressed extension, version 1.9 .
 
 *_Preface to Version 2.0_*
 
@@ -312,45 +312,45 @@ extensions.
 encoding more efficient.
 * The base ISA has been defined to have a little-endian memory system,
 with big-endian or bi-endian as non-standard variants.
-* Load-Reserved/Store-Conditional (LR/SC) instructions have been added
+* Load-Reserved/Store-Conditional (`LR/SC`) instructions have been added
 in the atomic instruction extension.
-* AMOs and LR/SC can support the release consistency model.
-* The FENCE instruction provides finer-grain memory and I/O orderings.
-* An AMO for fetch-and-XOR (AMOXOR) has been added, and the encoding for
-AMOSWAP has been changed to make room.
-* The AUIPC instruction, which adds a 20-bit upper immediate to the PC,
-replaces the RDNPC instruction, which only read the current PC value.
+* `AMOs` and `LR/SC` can support the release consistency model.
+* The `FENCE` instruction provides finer-grain memory and I/O orderings.
+* An `AMO` for fetch-and-`XOR` (`AMOXOR`) has been added, and the encoding for
+`AMOSWAP` has been changed to make room.
+* The `AUIPC` instruction, which adds a 20-bit upper immediate to the `PC`,
+replaces the `RDNPC` instruction, which only read the current `PC` value.
 This results in significant savings for position-independent code.
-* The JAL instruction has now moved to the U-Type format with an
-explicit destination register, and the J instruction has been dropped
-being replaced by JAL with _rd_='x0'. This removes the only instruction
-with an implicit destination register and removes the J-Type instruction
-format from the base ISA. There is an accompanying reduction in JAL
+* The `JAL` instruction has now moved to the `U-Type` format with an
+explicit destination register, and the `J` instruction has been dropped
+being replaced by `JAL` with _rd_=`x0`. This removes the only instruction
+with an implicit destination register and removes the `J-Type` instruction
+format from the base ISA. There is an accompanying reduction in `JAL`
 reach, but a significant reduction in base ISA complexity.
-* The static hints on the JALR instruction have been dropped. The hints
+* The static hints on the `JALR` instruction have been dropped. The hints
 are redundant with the _rd_ and _rs1_ register specifiers for code
 compliant with the standard calling convention.
-* The JALR instruction now clears the lowest bit of the calculated
+* The `JALR` instruction now clears the lowest bit of the calculated
 target address, to simplify hardware and to allow auxiliary information
 to be stored in function pointers.
-* The MFTX.S and MFTX.D instructions have been renamed to FMV.X.S and
-FMV.X.D, respectively. Similarly, MXTF.S and MXTF.D instructions have
-been renamed to FMV.S.X and FMV.D.X, respectively.
-* The MFFSR and MTFSR instructions have been renamed to FRCSR and FSCSR,
-respectively. FRRM, FSRM, FRFLAGS, and FSFLAGS instructions have been
+* The `MFTX.S` and `MFTX.D` instructions have been renamed to `FMV.X.S` and
+`FMV.X.D`, respectively. Similarly, `MXTF.S` and `MXTF.D` instructions have
+been renamed to `FMV.S.X` and `FMV.D.X`, respectively.
+* The `MFFSR` and `MTFSR` instructions have been renamed to `FRCSR` and `FSCSR`,
+respectively. `FRRM`, `FSRM`, `FRFLAGS`, and `FSFLAGS` instructions have been
 added to individually access the rounding mode and exception flags
-subfields of the 'fcsr'.
-* The FMV.X.S and FMV.X.D instructions now source their operands from
+subfields of the `fcsr`.
+* The `FMV.X.S` and `FMV.X.D` instructions now source their operands from
 _rs1_, instead of _rs2_. This change simplifies datapath design.
-* FCLASS.S and FCLASS.D floating-point classify instructions have been
+* `FCLASS.S` and `FCLASS.D` floating-point classify instructions have been
 added.
 * A simpler NaN generation and propagation scheme has been adopted.
-* For RV32I, the system performance counters have been extended to
+* For `RV32I`, the system performance counters have been extended to
 64-bits wide, with separate read access to the upper and lower 32 bits.
-* Canonical NOP and MV encodings have been defined.
+* Canonical `NOP` and `MV` encodings have been defined.
 * Standard instruction-length encodings have been defined for 48-bit,
 64-bit, and latexmath:[$>$]64-bit instructions.
-* Description of a 128-bit address space variant, RV128, has been added.
+* Description of a 128-bit address space variant, `RV128`, has been added.
 * Major opcodes in the 32-bit base instruction format have been
 allocated for user-defined custom extensions.
 * A typographical error that suggested that stores source their data