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| author | wmat <wmat@riscv.org> | 2024-04-04 10:37:59 -0400 |
|---|---|---|
| committer | wmat <wmat@riscv.org> | 2024-04-04 10:37:59 -0400 |
| commit | c7ce7b31c95b570076ab718e2c13ece6050a663d (patch) | |
| tree | a4480358a881c6935e1a9b2515f3a2e85a6d51f4 /src/cmo.adoc | |
| parent | 58220614a5f9acbbdec105b7cadb5f04bbb7b47f (diff) | |
| download | riscv-isa-manual-c7ce7b31c95b570076ab718e2c13ece6050a663d.zip riscv-isa-manual-c7ce7b31c95b570076ab718e2c13ece6050a663d.tar.gz riscv-isa-manual-c7ce7b31c95b570076ab718e2c13ece6050a663d.tar.bz2 | |
Adding *tval address explanation text.
Adding *tval address explanation text. This is Issue #1317.
Diffstat (limited to 'src/cmo.adoc')
| -rw-r--r-- | src/cmo.adoc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cmo.adoc b/src/cmo.adoc index 705166a..d4f2441 100644 --- a/src/cmo.adoc +++ b/src/cmo.adoc @@ -381,6 +381,8 @@ exceptions and shall not access any caches or memory. During address translation, the instruction does _not_ check the accessed and dirty bits and neither raises an exception nor sets the bits. +When a page fault, guest-page fault, or access fault exception is taken, the relevant *tval CSR is written with the faulting effective address (i.e. the same faulting address value as for other causes of these exceptions). + [NOTE] ==== _Like a load or store instruction, a CMO instruction may or may not be permitted |