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| author | Andrew Waterman <andrew@sifive.com> | 2022-08-29 12:07:55 -0700 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-11-04 14:00:57 -0400 |
| commit | 73b8ce78c6efce48eed548007abff5a87a0044db (patch) | |
| tree | e123c9a9f08462c82ab0faba2bf1a1419a3d1b22 /src/c.tex | |
| parent | 2c91435e24d6b2a78147e0c3eefe546afd97bd6d (diff) | |
| download | riscv-isa-manual-73b8ce78c6efce48eed548007abff5a87a0044db.zip riscv-isa-manual-73b8ce78c6efce48eed548007abff5a87a0044db.tar.gz riscv-isa-manual-73b8ce78c6efce48eed548007abff5a87a0044db.tar.bz2 | |
Standardize on {\tt pc}, rather than PC
We were using a mix of the two, with a bias towards the former.
Resolves #887
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -697,7 +697,7 @@ with $\textit{rs1}{=}\texttt{x0}$ corresponds to the C.EBREAK instruction. \begin{commentary} Strictly speaking, C.JALR does not expand exactly to a base RVI -instruction as the value added to the PC to form the link address is 2 +instruction as the value added to the {\tt pc} to form the link address is 2 rather than 4 as in the base ISA, but supporting both offsets of 2 and 4 bytes is only a very minor change to the base microarchitecture. \end{commentary} |