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| author | Andrew Waterman <andrew@sifive.com> | 2024-04-26 19:16:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-04-26 19:16:13 -0700 |
| commit | c8773d5ad3b6d2b4bb92ed0c5ea26abac5b52c68 (patch) | |
| tree | 97f72aa9c0cf0d14656b0db163d909d3427dd03b /src/c-st-ext.adoc | |
| parent | 3d703f3f2d8fb5ebdbc8ee6be508661c318d451b (diff) | |
| download | riscv-isa-manual-c8773d5ad3b6d2b4bb92ed0c5ea26abac5b52c68.zip riscv-isa-manual-c8773d5ad3b6d2b4bb92ed0c5ea26abac5b52c68.tar.gz riscv-isa-manual-c8773d5ad3b6d2b4bb92ed0c5ea26abac5b52c68.tar.bz2 | |
Don't hyphenate "sign extension" when used as noun
Diffstat (limited to 'src/c-st-ext.adoc')
| -rw-r--r-- | src/c-st-ext.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index b4fe138..97aca5f 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -202,7 +202,7 @@ The formats were designed to keep bits for the two register source specifiers in the same place in all instructions, while the destination register field can move. When the full 5-bit destination register specifier is present, it is in the same place as in the 32-bit RISC-V -encoding. Where immediates are sign-extended, the sign-extension is +encoding. Where immediates are sign-extended, the sign extension is always from bit 12. Immediate fields have been scrambled, as in the base specification, to reduce the number of immediate muxes required. [NOTE] |