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author | Bill Traynor <wmat@riscv.org> | 2023-01-31 16:17:53 -0500 |
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committer | Bill Traynor <wmat@riscv.org> | 2023-01-31 16:17:53 -0500 |
commit | c44b7380ae9603f1d50f608c4a0423f7ce42a5c0 (patch) | |
tree | 8bb3ba87a302133fc5726f20a8bd80e942c14049 /src/c-st-ext.adoc | |
parent | a774047d0d67b2a3320215fd9f18075c39c05c67 (diff) | |
download | riscv-isa-manual-c44b7380ae9603f1d50f608c4a0423f7ce42a5c0.zip riscv-isa-manual-c44b7380ae9603f1d50f608c4a0423f7ce42a5c0.tar.gz riscv-isa-manual-c44b7380ae9603f1d50f608c4a0423f7ce42a5c0.tar.bz2 |
Formatting Table 33
Formatting Table 33
Diffstat (limited to 'src/c-st-ext.adoc')
-rw-r--r-- | src/c-st-ext.adoc | 46 |
1 files changed, 35 insertions, 11 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index df34cc9..e5cf6d2 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -912,18 +912,42 @@ microarchitectural hints (see <<rvc-hints, Section 18.7>>). [[rvcopcodemap]] .RVC opcode map instructions. -[cols="20%,6%,8%,6%,6%,6%,6%,6%,6%,5%] +[cols=">,^,^,^,^,^,^,^,^,^,^,<] |=== -|inst[15:13] .2+^.>s|000 .2+^.>s|001 .2+^.>s|010 .2+^.>s|011 .2+^.>s|100 .2+^.>s|101 .2+^.>s|110 .2+^.>s|111 .2+^.>s| -|inst[1:0] - -|00|ADDI4SPN |FLD FLD LQ | LW | FLW LD LD | _Reserved_ | FSD FSD SQSW | SW | FSW SD SD | RV32 RV64 RV128 - -|01 |ADDI |JAL ADDIW ADDIW |LI |LUI/ADDI16SP |MISC-ALU |J |BEQZ |BNEZ |RV32 RV64 RV128 - -|10 |SLLI |FLDSP FLDSP LDSP |LWSP |FLWSP LDSP LDSP |J[AL]R/MV/ADD |FSDSP FSDSP SQSP|SWSP |FSWSP SDSP SDSP|RV32 RV6 RV128 - -|11 9+|latexmath:[$>$]16b +2+>|inst[15:13] .2+^.^s|000 .2+^.^s|001 .2+^.^s|010 .2+^.^s|011 .2+^.^s|100 .2+^.^s|101 .2+^.^s|110 .2+^.^s|111 .2+^.>s| +2+>|inst[1:0] + +2+>.^|00 .^|ADDI4SPN ^.^|FLD + +FLD + +LQ ^.^| LW ^.^| FLW + +LD + +LD ^.^| _Reserved_ ^.^| FSD + +FSD + +SQSW ^.^| SW ^.^| FSW + +SD + +SD ^.^| RV32 + +RV64 + +RV128 + +2+>.^|01 ^.^|ADDI ^.^|JAL + +ADDIW + +ADDIW ^.^|LI ^.^|LUI/ADDI16SP ^.^|MISC-ALU ^.^|J ^.^|BEQZ ^.^|BNEZ ^.^|RV32 + +RV64 + +RV128 + +2+>.^|10 ^.^|SLLI ^.^|FLDSP + +FLDSP + +LDSP ^.^|LWSP ^.^|FLWSP + +LDSP + +LDSP ^.^|J[AL]R/MV/ADD ^.^|FSDSP + +FSDSP + +SQSP ^.^|SWSP ^.^|FSWSP + +SDSP + +SDSP ^.^|RV32 + +RV6 + +RV128 + +2+>.^|11 9+^|>16b |=== <<rvc-instr-table0>>, <<rvc-instr-table1>>, and <<rvc-instr-table2>> list the RVC instructions. |