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| author | Bill Traynor <wmat@riscv.org> | 2023-02-09 13:08:46 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-02-09 13:08:46 -0500 |
| commit | a657ec67516cd0847cc59d9ef224d5c8aaec7d39 (patch) | |
| tree | f4fa1d7d16f9274ceadacb02666f0baa570113fd /src/c-st-ext.adoc | |
| parent | 4c8c04caed4c04f5ec65b88c18b8da756de47dd2 (diff) | |
| download | riscv-isa-manual-a657ec67516cd0847cc59d9ef224d5c8aaec7d39.zip riscv-isa-manual-a657ec67516cd0847cc59d9ef224d5c8aaec7d39.tar.gz riscv-isa-manual-a657ec67516cd0847cc59d9ef224d5c8aaec7d39.tar.bz2 | |
Added rvc-opcodemap table back in.
Added rvc-opcodemap table back in.
Diffstat (limited to 'src/c-st-ext.adoc')
| -rw-r--r-- | src/c-st-ext.adoc | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index 84c655a..0eab2c7 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -913,8 +913,44 @@ microarchitectural hints (see <<rvc-hints, Section 18.7>>). <<< [[rvcopcodemap]] -//include::images/bytefield/rvc-opcode-map.png[] -//include::images/bytefield/rvc-opcode-map.jpg[] +.RVC opcode map instructions. +[cols=">,^,^,^,^,^,^,^,^,^,^,<] +|=== +2+>|inst[15:13] .2+^.^s|000 .2+^.^s|001 .2+^.^s|010 .2+^.^s|011 .2+^.^s|100 .2+^.^s|101 .2+^.^s|110 .2+^.^s|111 .2+^.>s| +2+>|inst[1:0] + +2+>.^|00 .^|ADDI4SPN ^.^|FLD + +FLD + +LQ ^.^| LW ^.^| FLW + +LD + +LD ^.^| _Reserved_ ^.^| FSD + +FSD + +SQSW ^.^| SW ^.^| FSW + +SD + +SD ^.^| RV32 + +RV64 + +RV128 + +2+>.^|01 ^.^|ADDI ^.^|JAL + +ADDIW + +ADDIW ^.^|LI ^.^|LUI/ADDI16SP ^.^|MISC-ALU ^.^|J ^.^|BEQZ ^.^|BNEZ ^.^|RV32 + +RV64 + +RV128 + +2+>.^|10 ^.^|SLLI ^.^|FLDSP + +FLDSP + +LDSP ^.^|LWSP ^.^|FLWSP + +LDSP + +LDSP ^.^|J[AL]R/MV/ADD ^.^|FSDSP + +FSDSP + +SQSP ^.^|SWSP ^.^|FSWSP + +SDSP + +SDSP ^.^|RV32 + +RV6 + +RV128 + +2+>.^|11 9+^|>16b +|=== <<rvc-instr-table0>>, <<rvc-instr-table1>>, and <<rvc-instr-table2>> list the RVC instructions. |