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| author | Bill Traynor <wmat@riscv.org> | 2023-02-01 11:07:32 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-02-01 11:07:32 -0500 |
| commit | 0aa8a751bd7ca28ad95c20165bac1eac7fe022b6 (patch) | |
| tree | 9ac241a5b38f40673fb62fe2b5f1e384b759da87 /src/c-st-ext.adoc | |
| parent | 7a01cfd95fb0904d86b1b226b92e426eb92b83fe (diff) | |
| download | riscv-isa-manual-0aa8a751bd7ca28ad95c20165bac1eac7fe022b6.zip riscv-isa-manual-0aa8a751bd7ca28ad95c20165bac1eac7fe022b6.tar.gz riscv-isa-manual-0aa8a751bd7ca28ad95c20165bac1eac7fe022b6.tar.bz2 | |
Table 34 formatting
Cleaned up Table 34 and reformatted
Added proper prime marks
Diffstat (limited to 'src/c-st-ext.adoc')
| -rw-r--r-- | src/c-st-ext.adoc | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index 2734964..584f6d6 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -956,36 +956,36 @@ RV128 [[rvc-instr-table0]] .Instruction listing for RVC, Quadrant 0 -[%header,format+DSV,separator=!,cols="10%,12%,12%,12%,6%,5%,41%"] +[%header,format+DSV,separator=!,cols="^10%,^12%,^12%,^12%,^6%,^5%,<41%"] !=== ^!15 14 13 3+^! 12 11 10 9 8 7 6 5 ^!4 3 2 ^! 1 0 ! -!000 3+!0 ! 0 !00 !_Illegal instruction_ +!000 3+^!0 ! 0 !00 <!_Illegal instruction_ -!000 3+!nzuimm[5:4|9:6|2|3] ! rd' !00 !C.ADDI4SPN _(RES,nzuimm=0)_ +!000 3+^!nzuimm[5:4|9:6|2|3] ! rd′ !00 <!C.ADDI4SPN _(RES,nzuimm=0)_ -!001!uimm[5:3] !rs1 l' !uimm[7:6] !rd' !00 !C.FLD _(RV32/64)_ +!001!uimm[5:3] !rs1′ !uimm[7:6] !rd′ !00 !C.FLD _(RV32/64)_ -!001!uimm[5:4|8] !rs1 l' !uimm[7:6] !rd' !00 !C.LQ _(RV128)_ +!001!uimm[5:4|8] !rs1′ !uimm[7:6] !rd′ !00 !C.LQ _(RV128)_ -!010!uimm[5:3] !rs1 l' !uimm[2|6] !rd' !00 !C.LW +!010!uimm[5:3] !rs1′ !uimm[2|6] !rd′ !00 !C.LW -!011!uimm[5:3] !rs1 l' !uimm[2|6] !rd' !00 !C.FLW _(RV32)_ +!011!uimm[5:3] !rs1′ !uimm[2|6] !rd′ !00 !C.FLW _(RV32)_ -!011!uimm[5:3] !rs1 l' !uimm[7:6] !rd' !00 !C.LD _(RV64/128)_ +!011!uimm[5:3] !rs1′ !uimm[7:6] !rd′ !00 !C.LD _(RV64/128)_ !100 4+!— !00 !_Reserved_ -!101!uimm[5:3] !rs1 l' !uimm[7:6] !rs2' !00 !C.FSD _(RV32/64)_ +!101!uimm[5:3] !rs1′ !uimm[7:6] !rs2′ !00 !C.FSD _(RV32/64)_ -!101 !uimm[5:4|8] !rs1 l' !uimm[7:6] !rs2' !00 !C.SQ _(RV128)_ +!101 !uimm[5:4|8] !rs1′ !uimm[7:6] !rs2′ !00 !C.SQ _(RV128)_ -!110!uimm[5:3] !rs1 l' ! uimm[2|6] !rs2' !00 !C.SW +!110!uimm[5:3] !rs1′ ! uimm[2|6] !rs2′ !00 !C.SW -!111!uimm[5:3] !rs1 l' !uimm[2|6] !rs2' !00 !C.FSW _(RV32)_ +!111!uimm[5:3] !rs1′ !uimm[2|6] !rs2′ !00 !C.FSW _(RV32)_ -!111!uimm[5:3] !rs1 l' !uimm[7:6] !rs2' !00 !C.SD _(RV64/128)_ +!111!uimm[5:3] !rs1′ !uimm[7:6] !rs2′ !00 !C.SD _(RV64/128)_ !=== |