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author | Krste Asanovic <krste@MB1965.local> | 2017-05-06 15:21:16 +0100 |
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committer | Krste Asanovic <krste@MB1965.local> | 2017-05-06 15:21:16 +0100 |
commit | 07b35047789e34fd61db2603606a42a9a1808e04 (patch) | |
tree | 696abd405f55162376fb54017aa7e295b187064e /src/a.tex | |
parent | 469f83a48d592807691c56c522d666beeb6324ca (diff) | |
download | riscv-isa-manual-07b35047789e34fd61db2603606a42a9a1808e04.zip riscv-isa-manual-07b35047789e34fd61db2603606a42a9a1808e04.tar.gz riscv-isa-manual-07b35047789e34fd61db2603606a42a9a1808e04.tar.bz2 |
Updated to define and use hart more consistently.
Added warnings about changes to memory model.
Diffstat (limited to 'src/a.tex')
-rw-r--r-- | src/a.tex | 35 |
1 files changed, 22 insertions, 13 deletions
@@ -1,10 +1,19 @@ \chapter{``A'' Standard Extension for Atomic Instructions, Version 2.0} \label{atomics} +\begin{commentary} +This section is somewhat out of date as the RISC-V memory model is +currently under revision to ensure it can efficiently support current +programming language memory models. The revised base memory model +will contain further ordering constraints, including at least that +loads to the same address from the same hart cannot be reordered, and +that syntactic data dependencies between instructions are respected. +\end{commentary} + The standard atomic instruction extension is denoted by instruction subset name ``A'', and contains instructions that atomically read-modify-write memory to support synchronization between multiple -RISC-V threads running in the same memory space. The two forms of +RISC-V harts running in the same memory space. The two forms of atomic instruction provided are load-reserved/store-conditional instructions and atomic fetch-and-op memory instructions. Both types of atomic instruction support various memory consistency orderings @@ -31,7 +40,7 @@ To provide more efficient support for release consistency~\cite{Gharachorloo90memoryconsistency}, each atomic instruction has two bits, {\em aq} and {\em rl}, used to specify additional memory ordering constraints as viewed by other RISC-V -threads. The bits order accesses to one of the two address domains, +harts. The bits order accesses to one of the two address domains, memory or I/O, depending on which address domain the atomic instruction is accessing. No ordering constraint is implied to accesses to the other domain, and a FENCE instruction should be used @@ -40,16 +49,16 @@ to order across both domains. If both bits are clear, no additional ordering constraints are imposed on the atomic memory operation. If only the {\em aq} bit is set, the atomic memory operation is treated as an {\em acquire} access, i.e., -no following memory operations on this RISC-V thread can be observed +no following memory operations on this RISC-V hart can be observed to take place before the acquire memory operation. If only the {\em rl} bit is set, the atomic memory operation is treated as a {\em release} access, i.e., the release memory operation can not be observed to take place before any earlier memory operations on this -RISC-V thread. If both the {\em aq} and {\em rl} bits are set, the +RISC-V hart. If both the {\em aq} and {\em rl} bits are set, the atomic memory operation is {\em sequentially consistent} and cannot be observed to happen before any earlier memory operations or after any -later memory operations in the same RISC-V thread, and can only be -observed by any other thread in the same global order of all +later memory operations in the same RISC-V hart, and can only be +observed by any other hart in the same global order of all sequentially consistent atomic memory operations to the same address domain. @@ -164,7 +173,7 @@ that do not meet these constraints might complete on some attempts on some implementations, but there is no guarantee of eventual success. \begin{commentary} -One advantage of CAS is that it guarantees that some thread eventually +One advantage of CAS is that it guarantees that some hart eventually makes progress, whereas an LR/SC atomic sequence could livelock indefinitely on some systems. To avoid this concern, we added an architectural guarantee of forward progress to LR/SC atomic sequences. @@ -231,9 +240,9 @@ only take three instructions. \label{cas} \end{figure} -An SC instruction can never be observed by another RISC-V thread +An SC instruction can never be observed by another RISC-V hart before the immediately preceding LR. Due to the atomic nature of the -LR/SC sequence, no memory operations from any thread can be observed +LR/SC sequence, no memory operations from any hart can be observed to have occurred between the LR and a successful SC. The LR/SC sequence can be given acquire semantics by setting the {\em aq} bit on the SC instruction. The LR/SC sequence can be given release semantics @@ -245,7 +254,7 @@ operations. If neither bit is set on both LR and SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from -the same RISC-V thread. This can be appropriate when the LR/SC +the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation. \begin{commentary} @@ -329,11 +338,11 @@ bits) in the I/O space. To help implement multiprocessor synchronization, the AMOs optionally provide release consistency semantics. If the {\em aq} bit is set, -then no later memory operations in this RISC-V thread can be observed +then no later memory operations in this RISC-V hart can be observed to take place before the AMO. Conversely, if the {\em rl} bit is set, then other -RISC-V threads will not observe the AMO before memory accesses -preceding the AMO in this RISC-V thread. +RISC-V harts will not observe the AMO before memory accesses +preceding the AMO in this RISC-V hart. \begin{commentary} The AMOs were designed to implement the C11 and C++11 memory models |