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| author | Andrew Waterman <andrew@sifive.com> | 2024-07-23 19:57:20 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-24 02:57:20 +0000 |
| commit | fb235792a79a97b18b818bc0315737d08e231b35 (patch) | |
| tree | 7a1d6efde118a977136aacb8cee653c99dcf8ba5 | |
| parent | bc6a9b7cea1a8cf108d4c16fc6b68c18f50bdba1 (diff) | |
| download | riscv-isa-manual-fb235792a79a97b18b818bc0315737d08e231b35.zip riscv-isa-manual-fb235792a79a97b18b818bc0315737d08e231b35.tar.gz riscv-isa-manual-fb235792a79a97b18b818bc0315737d08e231b35.tar.bz2 | |
Define JR, RET pseudoinstructions (#1555)riscv-isa-release-fb23579-2024-07-24
Symmetric with defining J pseudoinstruction earlier in the same section.
Resolves #1253
| -rw-r--r-- | src/rv32.adoc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/rv32.adoc b/src/rv32.adoc index 1deda32..64949de 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -456,6 +456,12 @@ instruction following the jump (`pc`+4) is written to register _rd_. Register `x0` can be used as the destination if the result is not required. +Plain unconditional indirect jumps (assembler pseudoinstruction JR) are +encoded as a JALR with _rd_=`x0`. +Procedure returns in the standard calling convention (assembler +pseudoinstruction RET) are encoded as a JALR with _rd_=`x0`, _rs1_=`x1`, and +_imm_=0. + include::images/wavedrom/ct-unconditional-2.adoc[] [[ct-unconditional-2]] //.The indirect unconditional-jump instruction, JALR |