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author | Bill Traynor <wmat@riscv.org> | 2023-03-23 11:34:51 -0400 |
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committer | Bill Traynor <wmat@riscv.org> | 2023-03-23 11:34:51 -0400 |
commit | f7e20e1049fdd5f5144a48f97f4c1079526071f4 (patch) | |
tree | 2b2d6b7e8243d58d75bd2a2aea7719d6bfd1105a | |
parent | d282be168046b0c393123138fbab4be5e602d2bc (diff) | |
download | riscv-isa-manual-f7e20e1049fdd5f5144a48f97f4c1079526071f4.zip riscv-isa-manual-f7e20e1049fdd5f5144a48f97f4c1079526071f4.tar.gz riscv-isa-manual-f7e20e1049fdd5f5144a48f97f4c1079526071f4.tar.bz2 |
Adding vsip and vsie reg diags
Adding vsip and vsie reg diagrams
-rw-r--r-- | src/hypervisor.adoc | 30 | ||||
-rw-r--r-- | src/images/bytefield/vsiereg-standard.edn | 45 | ||||
-rw-r--r-- | src/images/bytefield/vsiereg.edn | 17 | ||||
-rw-r--r-- | src/images/bytefield/vsipreg-standard.edn | 45 | ||||
-rw-r--r-- | src/images/bytefield/vsipreg.edn | 17 |
5 files changed, 139 insertions, 15 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 8c59a27..7029a3f 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -853,32 +853,32 @@ store _as though_ V=1. The `vsip` and `vsie` registers are VSXLEN-bit read/write registers that are VS-mode’s versions of supervisor CSRs `sip` and `sie`, formatted as -shown in Figures link:#vsipreg[[vsipreg]] and link:#vsiereg[[vsiereg]] +shown in <<vsipreg>> and <<vsiereg>> respectively. When V=1, `vsip` and `vsie` substitute for the usual `sip` and `sie`, so instructions that normally read or modify `sip`/`sie` actually access `vsip`/`vsie` instead. However, interrupts directed to HS-level continue to be indicated in the HS-level `sip` register, not in `vsip`, when V=1. -@J + - + -VSXLEN + +[[vsipreg]] +.Virtual supervisor interrupt-pending register (`vsip`). +include::images/bytefield/vsipreg.edn[] -@J + - + -VSXLEN + +[[vsiereg]] +.Virtual supervisor interrupt-enable register (`vsie`). +include::images/bytefield/vsiereg.edn[] The standard portions (bits 15:0) of registers `vsip` and `vsie` are -formatted as shown in Figures link:#vsipreg-standard[[vsipreg-standard]] -and link:#vsiereg-standard[[vsiereg-standard]] respectively. +formatted as shown in <<vsipreg-standard>> +and <<vsiereg-standard>> respectively. -ScFcFcc & & & & & & + -& & & & & & + -& 1 & 3 & 1 & 3 & 1 & 1 + +[[vsipreg-standard]] +.Standard portion (bits 15:0) of `vsip`. +include::images/bytefield/vsipreg-standard.edn[] -ScFcFcc & & & & & & + -& & & & & & + -& 1 & 3 & 1 & 3 & 1 & 1 + +[[vsisreg-standard]] +.Standard portion (bits 15:0) of `vsie`. +include::images/bytefield/vsiereg-standard.edn[] When bit 10 of `hideleg` is zero, `vsip`.SEIP and `vsie`.SEIE are read-only zeros. Else, `vsip`.SEIP and `vsie`.SEIE are aliases of diff --git a/src/images/bytefield/vsiereg-standard.edn b/src/images/bytefield/vsiereg-standard.edn new file mode 100644 index 0000000..5039ae8 --- /dev/null +++ b/src/images/bytefield/vsiereg-standard.edn @@ -0,0 +1,45 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 17}]) +(def row-height 30 ) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 32) + +(draw-box nil {:span 6 :borders {}}) +(draw-box "15" {:borders {}}) +(draw-box nil {:span 4 :borders {}}) +(draw-box "10" {:borders {}}) +(draw-box "9" {:span 2 :borders {}}) +(draw-box "8" {:borders {}}) +(draw-box nil {:borders {}}) +(draw-box "6" {:borders {}}) +(draw-box "5" {:span 2 :borders {}}) +(draw-box "4" {:borders {}}) +(draw-box nil {:borders {}}) +(draw-box "2" {:borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "0" {:borders {}}) +(draw-box nil {:span 7 :borders {}}) + +(draw-box nil {:span 6 :borders {}}) +(draw-box "0" {:span 6}) +(draw-box "SEIE" {:span 2}) +(draw-box "0" {:span 3}) +(draw-box "STIE" {:span 2}) +(draw-box "0" {:span 3}) +(draw-box "SSIE" {:span 2}) +(draw-box "0") +(draw-box nil {:span 7 :borders {}}) + +(draw-box nil {:span 6 :borders {}}) +(draw-box "6" {:span 6 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "3" {:span 3 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "3" {:span 3 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "1" {:borders {}}) +(draw-box nil {:span 7 :borders {}}) +----
\ No newline at end of file diff --git a/src/images/bytefield/vsiereg.edn b/src/images/bytefield/vsiereg.edn new file mode 100644 index 0000000..70c9071 --- /dev/null +++ b/src/images/bytefield/vsiereg.edn @@ -0,0 +1,17 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 17}]) +(def row-height 30 ) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 32) + +(draw-box "VSXLEN-1" {:span 16 :text-anchor "start" :borders {}}) +(draw-box "0" {:span 16 :text-anchor "end" :borders {}}) + +(draw-box "Interrupts" {:span 16 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}}) +(draw-box (text "(WARL)" {:font-weight "bold"}) {:span 16 :text-anchor "start" :borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}}) + +(draw-box "VSXLEN" {:span 32 :borders {}}) +----
\ No newline at end of file diff --git a/src/images/bytefield/vsipreg-standard.edn b/src/images/bytefield/vsipreg-standard.edn new file mode 100644 index 0000000..00cb4ec --- /dev/null +++ b/src/images/bytefield/vsipreg-standard.edn @@ -0,0 +1,45 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 17}]) +(def row-height 30 ) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 32) + +(draw-box nil {:span 6 :borders {}}) +(draw-box "15" {:borders {}}) +(draw-box nil {:span 4 :borders {}}) +(draw-box "10" {:borders {}}) +(draw-box "9" {:span 2 :borders {}}) +(draw-box "8" {:borders {}}) +(draw-box nil {:borders {}}) +(draw-box "6" {:borders {}}) +(draw-box "5" {:span 2 :borders {}}) +(draw-box "4" {:borders {}}) +(draw-box nil {:borders {}}) +(draw-box "2" {:borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "0" {:borders {}}) +(draw-box nil {:span 7 :borders {}}) + +(draw-box nil {:span 6 :borders {}}) +(draw-box "0" {:span 6}) +(draw-box "SEIP" {:span 2}) +(draw-box "0" {:span 3}) +(draw-box "STIP" {:span 2}) +(draw-box "0" {:span 3}) +(draw-box "SSIP" {:span 2}) +(draw-box "0") +(draw-box nil {:span 7 :borders {}}) + +(draw-box nil {:span 6 :borders {}}) +(draw-box "6" {:span 6 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "3" {:span 3 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "3" {:span 3 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "1" {:borders {}}) +(draw-box nil {:span 7 :borders {}}) +----
\ No newline at end of file diff --git a/src/images/bytefield/vsipreg.edn b/src/images/bytefield/vsipreg.edn new file mode 100644 index 0000000..70c9071 --- /dev/null +++ b/src/images/bytefield/vsipreg.edn @@ -0,0 +1,17 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 17}]) +(def row-height 30 ) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 32) + +(draw-box "VSXLEN-1" {:span 16 :text-anchor "start" :borders {}}) +(draw-box "0" {:span 16 :text-anchor "end" :borders {}}) + +(draw-box "Interrupts" {:span 16 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}}) +(draw-box (text "(WARL)" {:font-weight "bold"}) {:span 16 :text-anchor "start" :borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}}) + +(draw-box "VSXLEN" {:span 32 :borders {}}) +----
\ No newline at end of file |