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| author | Bill Traynor <wmat@riscv.org> | 2022-11-27 15:58:28 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-11-27 15:58:28 -0500 |
| commit | df7e73f13edd59da2434f48addc67cf12c1ac204 (patch) | |
| tree | df9a2cf5fd691baa3eab3b8e0bff8f26e2b60263 | |
| parent | b6f6a2da932cc7e2b5be7a01e4e2efd42bd10605 (diff) | |
| download | riscv-isa-manual-df7e73f13edd59da2434f48addc67cf12c1ac204.zip riscv-isa-manual-df7e73f13edd59da2434f48addc67cf12c1ac204.tar.gz riscv-isa-manual-df7e73f13edd59da2434f48addc67cf12c1ac204.tar.bz2 | |
Updating conversion issues.
Updating conversion issues.
| -rw-r--r-- | src/rv32.adoc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/rv32.adoc b/src/rv32.adoc index ba02728..5a2fae3 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -265,11 +265,11 @@ on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches. Overflow checking for unsigned addition requires only a single additional branch instruction after the addition: -`add t0, t1, t2; bltu t0, t1, overflow`. +'add t0, t1, t2; bltu t0, t1, overflow'. -For signed addition, if one operand’s sign is known, overflow checking +For signed addition, if one operand's sign is known, overflow checking requires only a single branch after the addition: -`addi t0, t1, +imm; blt t0, t1, overflow`. This covers the common case +'addi t0, t1, +imm; blt t0, t1, overflow'. This covers the common case of addition with an immediate operand. For general signed addition, three additional instructions after the |