diff options
| author | Shih-Sheng Yang <james1qaz2wsx12qw@gmail.com> | 2023-09-02 04:03:59 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-01 13:03:59 -0700 |
| commit | de9c2a8f6ef977a21785b59eb755dd26e1f0db27 (patch) | |
| tree | df824c349a8645b0387032aa340284a059973d52 | |
| parent | ee240a4e33ab4d64f300274532a3afa6e33dbd51 (diff) | |
| download | riscv-isa-manual-de9c2a8f6ef977a21785b59eb755dd26e1f0db27.zip riscv-isa-manual-de9c2a8f6ef977a21785b59eb755dd26e1f0db27.tar.gz riscv-isa-manual-de9c2a8f6ef977a21785b59eb755dd26e1f0db27.tar.bz2 | |
Update f-st-ext.adoc (#1106)
| -rw-r--r-- | src/f-st-ext.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc index 0e27348..380f471 100644 --- a/src/f-st-ext.adoc +++ b/src/f-st-ext.adoc @@ -157,7 +157,7 @@ arisen on any floating-point arithmetic instruction since the field was last reset by software, as shown in <<bitdef>>. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag. -(((floating-point, excpetion flag))) +(((floating-point, exception flag))) [[bitdef]] .Accrued exception flag encoding. |