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authorAndrew Waterman <andrew@sifive.com>2024-01-09 15:23:36 -0800
committerAndrew Waterman <andrew@sifive.com>2024-01-09 15:23:52 -0800
commitcae8e5fff6db7c939f11af91915ed2c8dde2582d (patch)
tree7047428445baf51a9606132bf37f38414f8b7c59
parent337aab689e4f8fb54590b37017e0c38fed444bca (diff)
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Fix an tex->adoc translation bug
-rw-r--r--src/supervisor.adoc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index 15a7768..0bbd783 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -103,7 +103,7 @@ destination register.
If UXLEN latexmath:[$<$] SXLEN, user-mode instruction-fetch addresses
and load and store effective addresses are taken modulo
latexmath:[$2^{\text{UXLEN}}$]. For example, when UXLEN=32 and SXLEN=64,
-user-mode memory accesses reference the lowest of the address space.
+user-mode memory accesses reference the lowest 4 GiB of the address space.
[[sum]]
===== Memory Privilege in `sstatus` Register