Merge pull request #1494 from riscv/hint-xlen

Relax behavior of some HINTs when MXLEN > XLEN

3 files changed, 30 insertions, 0 deletions

diff --git a/src/machine.adoc b/src/machine.adoc
index ff36ecc..fa22146 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -581,6 +581,21 @@ always be a software bug, but machine operation is well-defined even in
 this case.
 ====
 
+Some HINT instructions are encoded as integer computational instructions that
+overwrite their destination register with its current value, e.g.,
+`c.addi x8, 0`.
+When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the
+destination register not all equal to bit XLEN-1, it is implementation-defined
+whether bits MXLEN..XLEN of the destination register are unchanged or are
+overwritten with copies of bit XLEN-1.
+
+NOTE: This definition allows implementations to elide register writeback for
+some HINTs, while allowing them to execute other HINTs in the same manner as
+other integer computational instructions.
+The implementation choice is observable only by privilege modes with an XLEN
+setting greater than the current XLEN; it is invisible to the current
+privilege mode.
+
 ===== Memory Privilege in `mstatus` Register
 
 The MPRV (Modify PRiVilege) bit modifies the _effective privilege mode_,
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc
index 278498d..4a49e29 100644
--- a/src/priv-preface.adoc
+++ b/src/priv-preface.adoc
@@ -93,6 +93,7 @@ implemented.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
 * Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
+* Relaxed behavior of some HINTs when MXLEN > XLEN.
 
 Finally, the following clarifications and document improvments have been made
 since the last document release:
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index daecbc2..0a098be 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -149,6 +149,20 @@ and load and store effective addresses are taken modulo
 latexmath:[$2^{\text{UXLEN}}$]. For example, when UXLEN=32 and SXLEN=64,
 user-mode memory accesses reference the lowest 4 GiB of the address space.
 
+Some HINT instructions are encoded as integer computational instructions that
+overwrite their destination register with its current value, e.g.,
+`c.addi x8, 0`.
+When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the
+destination register not all equal to bit XLEN-1, it is implementation-defined
+whether bits SXLEN..XLEN of the destination register are unchanged or are
+overwritten with copies of bit XLEN-1.
+
+NOTE: This definition allows implementations to elide register writeback for
+some HINTs, while allowing them to execute other HINTs in the same manner as
+other integer computational instructions.
+The implementation choice is observable only by S-mode with SXLEN > UXLEN; it
+is invisible to U-mode.
+
 [[sum]]
 ===== Memory Privilege in `sstatus` Register