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| author | Bill Traynor <wmat@riscv.org> | 2022-11-27 14:49:22 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-11-27 14:49:22 -0500 |
| commit | ba15cf27fa41faf8612299765aee449e3dd9f254 (patch) | |
| tree | 77e8e435cbb9f8e2cf20fd5d34647826af31880f | |
| parent | d5b7441cfc02b85efef3d9f07b6980d9148b7bca (diff) | |
| download | riscv-isa-manual-ba15cf27fa41faf8612299765aee449e3dd9f254.zip riscv-isa-manual-ba15cf27fa41faf8612299765aee449e3dd9f254.tar.gz riscv-isa-manual-ba15cf27fa41faf8612299765aee449e3dd9f254.tar.bz2 | |
Changing bitfield size to make labels fit.
Updated imm[11] & imm[12] to 4 bits each to make their text fit.
| -rw-r--r-- | src/images/wavedrom/immediate_variants.adoc | 4 | ||||
| -rw-r--r-- | src/rv32.adoc | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/images/wavedrom/immediate_variants.adoc b/src/images/wavedrom/immediate_variants.adoc index cb63f57..f3c6179 100644 --- a/src/images/wavedrom/immediate_variants.adoc +++ b/src/images/wavedrom/immediate_variants.adoc @@ -41,13 +41,13 @@ .... {reg: [ {bits: 7, name: 'opcode'}, - {bits: 1, name: 'imm[11]', type: 3}, + {bits: 4, name: 'imm[11]', type: 3}, {bits: 4, name: 'imm[4:1]', type: 3}, {bits: 3, name: 'funct3'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 6, name: 'imm[10:5]', type: 3}, - {bits: 1, name: 'imm[12]', type: 3} + {bits: 4, name: 'imm[12]', type: 3} ], config: {label: {right: 'B-Type'}}} .... diff --git a/src/rv32.adoc b/src/rv32.adoc index 23371ac..8fccaba 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -42,7 +42,7 @@ Most of the commentary for RV32I also applies to the RV64I base. integer ISA. For RV32I, the 32 `x` registers are each 32 bits wide, i.e., XLEN=32. Register `x0` is hardwired with all bits equal to 0. General purpose registers `x1`–`x31` hold values that various -instructions interpret as a collection of Boolean values, or as two’s +instructions interpret as a collection of Boolean values, or as two's complement signed binary integers or unsigned binary integers. There is one additional unprivileged register: the program counter `pc` @@ -50,7 +50,7 @@ holds the address of the current instruction. [[gprs]] .RISC-V base unprivileged integer register state. -[col[s="<|^|>"|option[s="header",width="50%",align="center"grid="none"] +[col[s="<|^|>"|option[s="header",width="50%",align="center"grid="rows"] |=== <| [.small]#XLEN-1#| >| [.small]#0# 3+^| [.small]#x0/zero# @@ -86,7 +86,7 @@ holds the address of the current instruction. 3+^| [.small]#x30# 3+^| [.small]#x31# 3+^| [.small]#XLEN# -| [.small]#31#| >| [.small]#0# +| [.small]#XLEN-1#| >| [.small]#0# 3+^| [.small]#pc# 3+^| [.small]#XLEN# |=== @@ -113,7 +113,7 @@ would arguably be sufficient for an integer ISA running compiled code, it is impossible to encode a complete ISA with 16 registers in 16-bit instructions using a 3-address format. Although a 2-address format would be possible, it would increase instruction count and lower efficiency. -We wanted to avoid intermediate instruction sizes (such as Xtensa’s +We wanted to avoid intermediate instruction sizes (such as Xtensa's 24-bit instructions) to simplify base hardware implementations, and once a 32-bit instruction size was adopted, it was straightforward to support 32 integer registers. A larger number of integer registers also helps |