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| author | Andrew Waterman <andrew@sifive.com> | 2020-09-30 00:04:29 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-09-30 00:04:29 -0700 |
| commit | 90c9bfb40cb95a6da5aa32f0da599fe881dd5d79 (patch) | |
| tree | b61eb7173fcb33d663f935a8269f375c4de37560 | |
| parent | 106ccea7e7221ebbf3f96471fc282d03eb337c5a (diff) | |
| download | riscv-isa-manual-90c9bfb40cb95a6da5aa32f0da599fe881dd5d79.zip riscv-isa-manual-90c9bfb40cb95a6da5aa32f0da599fe881dd5d79.tar.gz riscv-isa-manual-90c9bfb40cb95a6da5aa32f0da599fe881dd5d79.tar.bz2 | |
Disabling and reenabling extensions makes their state unspecified (#585)
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 2d1ce46..c2e2568 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -183,6 +183,10 @@ If an instruction that would write {\tt misa} increases IALIGN, and the subsequent instruction's address is not IALIGN-bit aligned, the write to {\tt misa} is suppressed, leaving {\tt misa} unchanged. +When software enables an extension that was previously disabled, then all +state uniquely associated with that extension is \unspecified, unless +otherwise specified by that extension. + \subsection{Machine Vendor ID Register {\tt mvendorid}} The {\tt mvendorid} CSR is a 32-bit read-only register providing |