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| author | Kersten Richter <kersten@riscv.org> | 2024-06-06 11:22:00 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-06 11:22:00 -0500 |
| commit | 81af58febb8850e7cbba5ee0ac51d34d81065e0e (patch) | |
| tree | dfdc746bae4437ffb639694e29096d42556302bc | |
| parent | 746bea9e3b7b838542eb2d9cdb0a99fb310e0fe1 (diff) | |
| download | riscv-isa-manual-81af58febb8850e7cbba5ee0ac51d34d81065e0e.zip riscv-isa-manual-81af58febb8850e7cbba5ee0ac51d34d81065e0e.tar.gz riscv-isa-manual-81af58febb8850e7cbba5ee0ac51d34d81065e0e.tar.bz2 | |
Update cr-register.adoc
found more
Signed-off-by: Kersten Richter <kersten@riscv.org>
| -rw-r--r-- | src/images/wavedrom/cr-register.adoc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.adoc index f4043d2..25f9752 100644 --- a/src/images/wavedrom/cr-register.adoc +++ b/src/images/wavedrom/cr-register.adoc @@ -38,7 +38,7 @@ .... {reg: [ {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rd`', type: 2}, + {bits: 3, name: 'rd', type: 2}, {bits: 8, name: 'imm', type: 3}, {bits: 3, name: 'funct3', type: 8}, ]} @@ -48,9 +48,9 @@ .... {reg: [ {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rd`', type: 2}, + {bits: 3, name: 'rd', type: 2}, {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1`', type: 4}, + {bits: 3, name: 'rs1', type: 4}, {bits: 3, name: 'imm', type: 3}, {bits: 3, name: 'funct3', type: 8}, ]} @@ -60,9 +60,9 @@ .... {reg: [ {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2`', type: 4}, + {bits: 3, name: 'rs2', type: 4}, {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1`', type: 4}, + {bits: 3, name: 'rs1', type: 4}, {bits: 3, name: 'imm', type: 3}, {bits: 3, name: 'funct3', type: 8}, ]} @@ -72,9 +72,9 @@ .... {reg: [ {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2`', type: 4}, + {bits: 3, name: 'rs2', type: 4}, {bits: 2, name: 'funct2', type: 8}, - {bits: 3, name: 'rd`/rs1`', type: 7}, + {bits: 3, name: 'rd`/rs1', type: 7}, {bits: 6, name: 'funct6', type: 8}, ]} .... @@ -84,7 +84,7 @@ {reg: [ {bits: 2, name: 'op', type: 8}, {bits: 5, name: 'offset', type: 3}, - {bits: 3, name: 'rd`/rs1`', type: 7}, + {bits: 3, name: 'rd`/rs1', type: 7}, {bits: 3, name: 'offset', type: 3}, {bits: 3, name: 'funct3', type: 8}, ]} |