More changes to match latex.

Removed table label.
Updated backticks to single quotes.

1 files changed, 8 insertions, 8 deletions

diff --git a/src/rv32.adoc b/src/rv32.adoc
index 9bc76f6..a48770e 100644
--- a/src/rv32.adoc
+++ b/src/rv32.adoc
@@ -462,7 +462,7 @@ required.
 
 include::images/wavedrom/ct-unconditional-2.adoc[]
 [[ct-unconditional-2]]
-.The indirect unconditional-jump instruction, JALR
+//.The indirect unconditional-jump instruction, JALR
 
 [NOTE]
 ====
@@ -487,7 +487,7 @@ there is potentially a slight loss of error checking in this case, in
 practice jumps to an incorrect instruction address will usually quickly
 raise an exception.
 
-When used with a base _rs1_=`x0`, JALR can be used to
+When used with a base _rs1_='x0', JALR can be used to
 implement a single instruction subroutine call to the lowest or highest
 address region from anywhere in the address space, which could be used
 to implement fast calls to a small runtime library. Alternatively, an
@@ -509,10 +509,10 @@ compressed instruction-set extension, C.
 Return-address prediction stacks are a common feature of
 high-performance instruction-fetch units, but require accurate detection
 of instructions used for procedure calls and returns to be effective.
-For RISC-V, hints as to the instructions’ usage are encoded implicitly
+For RISC-V, hints as to the instructions' usage are encoded implicitly
 via the register numbers used. A JAL instruction should push the return
-address onto a return-address stack (RAS) only when _rd_ is `x1` or
-`x5`. JALR instructions should push/pop a RAS as shown in <<rashints>>.
+address onto a return-address stack (RAS) only when _rd_ is 'x1' or
+'x5'. JALR instructions should push/pop a RAS as shown in <<rashints, Table 4>>.
 
 [[rashints]]
 .Return-address stack prediction hints encoded in the register operands of a JALR instruction.
@@ -539,9 +539,9 @@ instructions to guide return-address stack manipulation. We use implicit
 hinting tied to register numbers and the calling convention to reduce
 the encoding space used for these hints.
 
-When two different link registers (`x1` and `x5`) are given as _rs1_ and
+When two different link registers ('x1' and 'x5') are given as _rs1_ and
 _rd_, then the RAS is both popped and pushed to support coroutines. If
-_rs1_ and _rd_ are the same link register (either `x1` or `x5`), the RAS
+_rs1_ and _rd_ are the same link register (either 'x1' or 'x5'), the RAS
 is only pushed to enable macro-op fusion of the sequences:
 _lui ra, imm20; jalr ra, imm12(ra)_  and
 _auipc ra, imm20; jalr ra, imm12(ra)_
@@ -557,7 +557,7 @@ give the target address. The conditional branch range is
 
 include::images/wavedrom/ct-conditional.adoc[]
 [[ct-conditional]]
-.Conditional branches
+//.Conditional branches
 
 Branch instructions compare two registers. BEQ and BNE take the branch
 if registers _rs1_ and _rs2_ are equal or unequal respectively. BLT and