diff options
| author | Andrew Waterman <andrew@sifive.com> | 2024-04-26 19:08:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-04-26 19:08:37 -0700 |
| commit | 6d137a77e7e8619bf6eaf36a27674ec5bea08b21 (patch) | |
| tree | c9f63f5c3adea35ffc86236336c56566676c54fa | |
| parent | 0258a2fa843964eb864cfa7efb8a0387eaf7e763 (diff) | |
| download | riscv-isa-manual-6d137a77e7e8619bf6eaf36a27674ec5bea08b21.zip riscv-isa-manual-6d137a77e7e8619bf6eaf36a27674ec5bea08b21.tar.gz riscv-isa-manual-6d137a77e7e8619bf6eaf36a27674ec5bea08b21.tar.bz2 | |
Fix unintended indentation
| -rw-r--r-- | src/intro.adoc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intro.adoc b/src/intro.adoc index 78d7a34..47e3b7c 100644 --- a/src/intro.adoc +++ b/src/intro.adoc @@ -389,6 +389,7 @@ translation, it is common for each hart to be given a virtual address space that is largely or entirely its own. ==== (((memory access, implicit and explicit))) + Executing each RISC-V machine instruction entails one or more memory accesses, subdivided into _implicit_ and _explicit_ accesses. For each instruction executed, an _implicit_ memory read (instruction fetch) is |