Merge remote-tracking branch 'origin/main' into zc

12 files changed, 228 insertions, 64 deletions

diff --git a/marchid.md b/marchid.md
index 7f85b26..79f5e6d 100644
--- a/marchid.md
+++ b/marchid.md
@@ -59,3 +59,5 @@ WIV64         | Jesús Sanz del Rey              | [Jesús Sanz del Rey](mailto:
 RV6           | Nikola Lukić                    | [Nikola Lukić](mailto:lukicn@protonmail.com)                | 39               | https://github.com/kiclu/rv6
 ApogeoRV      | Gabriele Tripi                  | [Gabriele Tripi](mailto:tripi.gabriele2002@gmail.com)       | 40               | https://github.com/GabbedT/ApogeoRV
 MicroRV32      | AGRA, Group of Computer Architecture, University of Bremen | [RISC-V @ AGRA](mailto:riscv@informatik.uni-bremen.de)       | 41               | https://github.com/agra-uni-bremen/microrv32
+QEMU          | qemu.org                        | [QEMU Mailing List](mailto:qemu-riscv@nongnu.org)           | 42               | https://qemu.org
+KianV         | Hirosh Dabui                    | [Hirosh Dabui](mailto:hirosh@dabui.de)                      | 43               | https://github.com/splinedrive/kianRiscV
diff --git a/src/images/bytefield/miereg-standard.adoc b/src/images/bytefield/miereg-standard.adoc
index d069e9e..d4affab 100644
--- a/src/images/bytefield/miereg-standard.adoc
+++ b/src/images/bytefield/miereg-standard.adoc
@@ -6,10 +6,10 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 16)
-(draw-column-headers {:labels (reverse ["0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "" "" "15"])})
+(draw-column-headers {:labels (reverse ["0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15"])})
 
-(draw-box "0" {:span 4})
-(draw-box "MEIE" {:span 1})
+(draw-box "0" {:span 2})
+(draw-box (text "LCOFIE" {:font-size 10}) {:span 1})
 (draw-box "0" {:span 1})
 (draw-box "SEIE" {:span 1})
 (draw-box "0" {:span 1})
@@ -22,7 +22,7 @@
 (draw-box "SSIE" {:span 1})
 (draw-box "0" {:span 1})
 
-(draw-box "4" {:span 4 :borders {}})
+(draw-box "2" {:span 2 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
@@ -35,4 +35,5 @@
 (draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
-----
\ No newline at end of file
+(draw-box "1" {:span 1 :borders {}})
+----
diff --git a/src/images/bytefield/mipreg-standard.adoc b/src/images/bytefield/mipreg-standard.adoc
index 2b33776..e32e302 100644
--- a/src/images/bytefield/mipreg-standard.adoc
+++ b/src/images/bytefield/mipreg-standard.adoc
@@ -6,9 +6,11 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 16)
-(draw-column-headers {:labels (reverse ["0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "" "" "15"])})
+(draw-column-headers {:labels (reverse ["0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15"])})
 
-(draw-box "0" {:span 4})
+(draw-box "0" {:span 2})
+(draw-box (text "LCOFIP" {:font-size 10}) {:span 1})
+(draw-box "0" {:span 1})
 (draw-box "MEIP" {:span 1})
 (draw-box "0" {:span 1})
 (draw-box "SEIP" {:span 1})
@@ -22,7 +24,8 @@
 (draw-box "SSIP" {:span 1})
 (draw-box "0" {:span 1})
 
-(draw-box "4" {:span 4 :borders {}})
+(draw-box "2" {:span 2 :borders {}})
+(draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
@@ -35,4 +38,5 @@
 (draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
 (draw-box "1" {:span 1 :borders {}})
-----
\ No newline at end of file
+(draw-box "1" {:span 1 :borders {}})
+----
diff --git a/src/images/bytefield/siereg-standard.edn b/src/images/bytefield/siereg-standard.edn
index a4e2cf3..4a1fba6 100644
--- a/src/images/bytefield/siereg-standard.edn
+++ b/src/images/bytefield/siereg-standard.edn
@@ -8,8 +8,11 @@
 (def boxes-per-row 32)
 
 (draw-box nil {:span 7 :borders {}})
-(draw-box "15" {:span 3 :text-anchor "start" :borders {}})
-(draw-box "10" {:span 3 :text-anchor "end" :borders {}})
+(draw-box "15" {:text-anchor "start" :borders {}})
+(draw-box "14" {:text-anchor "end" :borders {}})
+(draw-box "13" {:span 2 :borders {}})
+(draw-box "12" {:text-anchor "start" :borders {}})
+(draw-box "10" {:text-anchor "end" :borders {}})
 (draw-box "9" {:span 2 :borders {}})
 (draw-box "8" {:text-anchor "start" :borders {}})
 (draw-box "6" {:text-anchor "end" :borders {}})
@@ -21,7 +24,9 @@
 (draw-box nil {:span 8 :borders {}})
 
 (draw-box nil {:span 7 :borders {}})
-(draw-box "0" {:span 6})
+(draw-box "0" {:span 2})
+(draw-box (text "LCOFIE" {:font-size 20}) {:span 2})
+(draw-box "0" {:span 2})
 (draw-box "SEIE" {:span 2})
 (draw-box "0" {:span 2})
 (draw-box "STIE" {:span 2})
@@ -31,7 +36,9 @@
 (draw-box nil {:span 8 :borders {}})
 
 (draw-box nil {:span 7 :borders {}})
-(draw-box "6" {:span 6 :borders {}})
+(draw-box "2" {:span 2 :borders {}})
+(draw-box "1" {:span 2 :borders {}})
+(draw-box "3" {:span 2 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "3" {:span 2 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
@@ -39,4 +46,4 @@
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "1" {:borders {}})
 (draw-box nil {:span 8 :borders {}})
-----
\ No newline at end of file
+----
diff --git a/src/images/bytefield/sipreg-standard.edn b/src/images/bytefield/sipreg-standard.edn
index 34bbfb4..440fd8f 100644
--- a/src/images/bytefield/sipreg-standard.edn
+++ b/src/images/bytefield/sipreg-standard.edn
@@ -8,8 +8,11 @@
 (def boxes-per-row 32)
 
 (draw-box nil {:span 7 :borders {}})
-(draw-box "15" {:span 3 :text-anchor "start" :borders {}})
-(draw-box "10" {:span 3 :text-anchor "end" :borders {}})
+(draw-box "15" {:text-anchor "start" :borders {}})
+(draw-box "14" {:text-anchor "end" :borders {}})
+(draw-box "13" {:span 2 :borders {}})
+(draw-box "12" {:text-anchor "start" :borders {}})
+(draw-box "10" {:text-anchor "end" :borders {}})
 (draw-box "9" {:span 2 :borders {}})
 (draw-box "8" {:text-anchor "start" :borders {}})
 (draw-box "6" {:text-anchor "end" :borders {}})
@@ -21,7 +24,9 @@
 (draw-box nil {:span 8 :borders {}})
 
 (draw-box nil {:span 7 :borders {}})
-(draw-box "0" {:span 6})
+(draw-box "0" {:span 2})
+(draw-box (text "LCOFIP" {:font-size 20}) {:span 2})
+(draw-box "0" {:span 2})
 (draw-box "SEIP" {:span 2})
 (draw-box "0" {:span 2})
 (draw-box "STIP" {:span 2})
@@ -31,7 +36,9 @@
 (draw-box nil {:span 8 :borders {}})
 
 (draw-box nil {:span 7 :borders {}})
-(draw-box "6" {:span 6 :borders {}})
+(draw-box "2" {:span 2 :borders {}})
+(draw-box "1" {:span 2 :borders {}})
+(draw-box "3" {:span 2 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "3" {:span 2 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
@@ -39,4 +46,4 @@
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "1" {:borders {}})
 (draw-box nil {:span 8 :borders {}})
-----
\ No newline at end of file
+----
diff --git a/src/machine.adoc b/src/machine.adoc
index 0469a15..d9e9042 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -1,9 +1,9 @@
 [[machine]]
-== Machine-Level ISA, Version 1.12
+== Machine-Level ISA, Version 1.13
 
 This chapter describes the machine-level operations available in
 machine-mode (M-mode), which is the highest privilege mode in a RISC-V
-system. M-mode is used for low-level access to a hardware platform and
+hart. M-mode is used for low-level access to a hardware platform and
 is the first mode entered at reset. M-mode can also be used to implement
 features that are too difficult or expensive to implement in hardware
 directly. The RISC-V machine-level ISA contains a common core that is
@@ -49,13 +49,13 @@ The `misa` CSR is MXLEN bits wide.
 The base width can be quickly ascertained using branches on the sign of
 the returned `misa` value, and possibly a shift left by one and a second
 branch on the sign. These checks can be written in assembly code without
-knowing the register width (MXLEN) of the machine. The base width is
+knowing the register width (MXLEN) of the hart. The base width is
 given by __MXLEN=2^MXL+4^__.
 
 The base width can also be found if `misa` is zero, by placing the
 immediate 4 in a register then shifting the register left by 31 bits at
-a time. If zero after one shift, then the machine is RV32. If zero after
-two shifts, then the machine is RV64, else RV128.
+a time. If zero after one shift, then the hart is RV32. If zero after
+two shifts, then the hart is RV64, else RV128.
 ====
 
 The Extensions field encodes the presence of the standard extensions,
@@ -176,7 +176,7 @@ _Reserved_ +
 Supervisor mode implemented +
 _Reserved_ +
 User mode implemented +
-"V" Vector extension implemented +
+Vector extension +
 _Reserved_ +
 Non-standard extensions present +
 _Reserved_ +
@@ -228,6 +228,13 @@ write to `misa` is suppressed, leaving `misa` unchanged.
 When software enables an extension that was previously disabled, then
 all state uniquely associated with that extension is UNSPECIFIED, unless otherwise specified by that extension.
 
+NOTE: Although one of the bits 25--0 in `misa` being set to 1 implies that
+the corresponding feature is implemented, the inverse is not necessarily
+true: one of these bits being clear does not necessarily imply that the
+corresponding feature is not implemented.  This follows from the fact that,
+when a feature is not implemented, the corresponding opcodes and CSRs become
+reserved, not necessarily illegal.
+
 ==== Machine Vendor ID Register `mvendorid`
 
 The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC
@@ -464,7 +471,7 @@ storage bit is required to represent either 00 or 11 in MPP.
 [[xlen-control]]
 ===== Base ISA Control in `mstatus` Register
 
-For RV64 systems, the SXL and UXL fields are *WARL* fields that control the
+For RV64 harts, the SXL and UXL fields are *WARL* fields that control the
 value of XLEN for S-mode and U-mode, respectively. The encoding of these
 fields is the same as the MXL field of `misa`, shown in
 <<misabase>>. The effective XLEN in S-mode and
@@ -778,7 +785,7 @@ If neither the `v` registers nor S-mode is implemented, then VS is
 read-only zero. If S-mode is implemented but the `v` registers are not,
 VS may optionally be read-only zero.
 
-In systems without additional user extensions requiring new state, the
+In harts without additional user extensions requiring new state, the
 XS field is read-only zero. Every additional extension with state
 provides a CSR field that encodes the equivalent of the XS states. The
 XS field represents a summary of all extensions' status as shown in
@@ -1134,16 +1141,16 @@ delegation register (`medeleg`) is a 64-bit read/write register.
 The machine interrupt delegation register (`mideleg`) is an MXLEN-bit
 read/write register.
 
-In systems with S-mode, the `medeleg` and `mideleg` registers must
+In harts with S-mode, the `medeleg` and `mideleg` registers must
 exist, and setting a bit in `medeleg` or `mideleg` will delegate the
 corresponding trap, when occurring in S-mode or U-mode, to the S-mode
-trap handler. In systems without S-mode, the `medeleg` and `mideleg`
+trap handler. In harts without S-mode, the `medeleg` and `mideleg`
 registers should not exist.
 
 [NOTE]
 ====
 In versions 1.9.1 and earlier , these registers existed but were
-hardwired to zero in M-mode only, or M/U without N systems. There is no
+hardwired to zero in M-mode only, or M/U without N harts. There is no
 reason to require they return zero in those cases, as the `misa`
 register indicates whether they exist.
 ====
@@ -1350,8 +1357,17 @@ the interrupt-pending and interrupt-enable bits for supervisor-level
 software interrupts. SSIP is writable in `mip` and may also be set to 1
 by a platform-specific interrupt controller.
 
+If the Sscofpmf extension is implemented, bits `mip`.LCOFIP and `mie`.LCOFIE
+are the interrupt-pending and interrupt-enable bits for local counter-overflow
+interrupts.
+LCOFIP is read-write in `mip` and reflects the occurrence of a local
+counter-overflow overflow interrupt request resulting from any of the
+`mhpmevent__n__`.OF bits being set.
+If the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are
+read-only zeros.
+
 Multiple simultaneous interrupts destined for M-mode are handled in the
-following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI.
+following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.
 
 [NOTE]
 ====
@@ -1393,7 +1409,7 @@ M-mode includes a basic hardware performance-monitoring facility. The
 `mcycle` CSR counts the number of clock cycles executed by the processor
 core on which the hart is running. The `minstret` CSR counts the number
 of instructions the hart has retired. The `mcycle` and `minstret`
-registers have 64-bit precision on all RV32 and RV64 systems.
+registers have 64-bit precision on all RV32 and RV64 harts.
 
 The counter registers have an arbitrary value after the hart is reset,
 and can be written with a given value. Any CSR write takes effect after
@@ -1457,9 +1473,9 @@ privilege mode (S-mode if implemented, otherwise U-mode).
 [NOTE]
 ====
 The counter-enable bits support two common use cases with minimal
-hardware. For systems that do not need high-performance timers and
+hardware. For harts that do not need high-performance timers and
 counters, machine-mode software can trap accesses and implement all
-features in software. For systems that need high-performance timers and
+features in software. For harts that need high-performance timers and
 counters but are not concerned with obfuscating the underlying hardware
 counters, the counters can be directly exposed to lower privilege modes.
 ====
@@ -1480,10 +1496,10 @@ loads to the memory-mapped `mtime` register, or emulate this
 functionality on behalf of less-privileged modes in M-mode software.
 ====
 
-In systems with U-mode, the `mcounteren` must be implemented, but all
+In harts with U-mode, the `mcounteren` must be implemented, but all
 fields are *WARL* and may be read-only zero, indicating reads to the
 corresponding counter will cause an illegal-instruction exception when
-executing in a less-privileged mode. In systems without U-mode, the
+executing in a less-privileged mode. In harts without U-mode, the
 `mcounteren` register should not exist.
 
 ==== Machine Counter-Inhibit CSR (`mcountinhibit`)
@@ -1681,7 +1697,7 @@ Machine external interrupt
 14-15 +
 &#8805;16
 |_Reserved_ +
-_Reserved for counter-overflow interrupt_ +
+Counter-overflow interrupt +
 _Reserved_ +
 _Designated for platform use_ 
 |0 +
@@ -1840,7 +1856,10 @@ this context, "data" encompasses all types of information used within a RISC-V
 hart. Upon a hardware error exception, the `__x__epc` register is set to the
 address of the instruction that attempted to access corrupted data, while the
 `__x__tval` register is set either to 0 or to the virtual address of an
-instruction fetch, load, or store that attempted to access corrupted data.
+instruction fetch, load, or store that attempted to access corrupted data. The
+priority of Hardware Error exception is implementation-defined, but any given
+occurrence is generally expected to be recognized at the point in the overall
+priority order at which the hardware error is discovered.
 ====
 
 ==== Machine Trap Value Register (`mtval`)
@@ -1878,7 +1897,7 @@ contain the virtual address of the portion of the access that caused the
 fault.
 
 If `mtval` is written with a nonzero value when an instruction
-access-fault or page-fault exception occurs on a system with
+access-fault or page-fault exception occurs on a hart with
 variable-length instructions, then `mtval` will contain the virtual
 address of the portion of the instruction that caused the fault, while
 `mepc` will point to the beginning of the instruction.
@@ -2878,7 +2897,7 @@ illegal.
 
 [NOTE]
 ====
-RV64 systems use `pmpcfg2`, rather than `pmpcfg1`, to hold
+RV64 harts use `pmpcfg2`, rather than `pmpcfg1`, to hold
 configurations for PMP entries 8-15. This design reduces the cost of
 supporting multiple MXLEN values, since the configurations for PMP
 entries 8-11 appear in `pmpcfg2`[31:0] for both RV32 and RV64.
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc
index 1071333..94ec43f 100644
--- a/src/priv-preface.adoc
+++ b/src/priv-preface.adoc
@@ -2,7 +2,7 @@
 = Preface
 
 This document describes the RISC-V privileged architecture. This
-release, version 20240131, contains the following versions of the RISC-V ISA
+release, version 20240213, contains the following versions of the RISC-V ISA
 modules:
 
 [%autowidth,float="center",align="center",cols="^,<,^",options="header",]
@@ -51,8 +51,9 @@ version 1.12:
 * Defined the `misa`.V field to reflect that the V extension has been
 implemented.
 * Defined the RV32-only `medelegh` and `hedelegh` CSRs.
-* Defined the misaligned atomicity granule PMA.
-* Reserved interrupt 13 for forthcoming counter-overflow interrupt extension.
+* Defined the misaligned atomicity granule PMA, superseding the proposed Zam
+  extension.
+* Allocated interrupt 13 for Sscofpmf LCOFI interrupt.
 * Defined hardware error and software check exception codes.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
@@ -68,6 +69,7 @@ in `menvcfg` and `henvcfg`.
 * Clarified that, for a given exception cause, `__x__tval` might sometimes
 be set to a nonzero value but sometimes not.
 * Clarified exception behavior of unimplemented or inaccessible CSRs.
+* Clarified that Svpbmt allows implementations to override additional PMAs.
 
 [.big]*_Preface to Version 20211203_*
 
diff --git a/src/riscv-privileged.adoc b/src/riscv-privileged.adoc
index 452f914..410aeab 100644
--- a/src/riscv-privileged.adoc
+++ b/src/riscv-privileged.adoc
@@ -2,9 +2,8 @@
 = The RISC-V Instruction Set Manual: Volume II: Privileged Architecture
 :description: Volume II - Privileged Architecture
 :company: RISC-V.org
-:author: Andrew waterman, waterman@eecs.berkeley.edu; Krste Asanović, krste@berkeley.edu; John Hauser, jh.riscv@jhauser.us, SiFive Inc., CS Division, EECS Department, University of California, Berkeley
-:revdate: Revised 20230731
-:revnumber: 20211203
+:revdate: Revised 20240213
+:revnumber: 20240213
 //:revremark: Pre-release version
 //development: assume everything can change
 //stable: assume everything could change
@@ -73,9 +72,6 @@ privileged specification version 1.9.1 released under following license: ©2010-
 Avižienis, 
 David Patterson, Krste Asanović. Creative Commons Attribution 4.0 International License._
 
-_Please cite as: “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211203”, Editors Andrew Waterman, Krste Asanović, and John Hauser, RISC-V
-International, December 2021._
-
 //the colophon allows for a section after the preamble that is part of the frontmatter and therefore not assigned a page number.
 //include::colophon.adoc[]
 //preface.tex
diff --git a/src/riscv-unprivileged.adoc b/src/riscv-unprivileged.adoc
index 9a0cf06..1ff9228 100644
--- a/src/riscv-unprivileged.adoc
+++ b/src/riscv-unprivileged.adoc
@@ -2,7 +2,6 @@
 = The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture
 :description: Unprivileged Architecture
 :company: RISC-V.org
-:authors: Editors: Andrew waterman, Krste Asanovic, SiFive, Inc., CS Division, EECS Department, University of California, Berkeley
 :revdate: Revised 20230723
 :revnumber: 20191214
 //:revremark: Pre-release version
@@ -51,16 +50,12 @@ endif::[]
 
 _Contributors to all versions of the spec in alphabetical order (please contact editors to suggest
 corrections): Arvind, Krste Asanović, Rimas Avižienis, Jacob Bachmeyer, Christopher F. Batten,
-Allen J. Baum, Alex Bradbury, Scott Beamer, Preston Briggs, Christopher Celio, Chuanhua
-Chang, David Chisnall, Paul Clayton, Palmer Dabbelt, Ken Dockser, Roger Espasa, Greg Favor,
-Shaked Flur, Stefan Freudenberger, Marc Gauthier, Andy Glew, Jan Gray, Michael Hamburg, John
+Allen J. Baum, Abel Bernabeu, Alex Bradbury, Scott Beamer, Preston Briggs, Christopher Celio, Chuanhua
+Chang, David Chisnall, Paul Clayton, Palmer Dabbelt, Ken Dockser, Paul Donahue, Aaron Durbin, Roger Espasa, Greg Favor, Shaked Flur, Stefan Freudenberger, Marc Gauthier, Andy Glew, Jan Gray, Michael Hamburg, John
 Hauser, David Horner, Bruce Hoult, Bill Huffman, Alexandre Joannou, Olof Johansson, Ben Keller,
-David Kruckemyer, Yunsup Lee, Paul Loewenstein, Daniel Lustig, Yatin Manerkar, Luc Maranget,
-Margaret Martonosi, Joseph Myers, Vijayanand Nagarajan, Rishiyur Nikhil, Jonas Oberhauser,
-Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Christopher Pulte, Jose Renau,
-Josh Scheid, Colin Schmidt, Peter Sewell, Susmit Sarkar, Michael Taylor, Wesley Terpstra, Matt
-Thomas, Tommy Thorn, Caroline Trippel, Ray VanDeWalker, Muralidaran Vijayaraghavan, Megan
-Wachs, Andrew Waterman, Robert Watson, Derek Williams, Andrew Wright, Reinoud Zandijk,
+David Kruckemyer, Tariq Kurd, Yunsup Lee, Paul Loewenstein, Daniel Lustig, Yatin Manerkar, Luc Maranget,
+Margaret Martonosi, Phil McCoy, Christoph Müllner, Joseph Myers, Vijayanand Nagarajan, Rishiyur Nikhil, Jonas Oberhauser, Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Christopher Pulte, Jose Renau,
+Josh Scheid, Colin Schmidt, Peter Sewell, Susmit Sarkar, Ved Shanbhogue, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Philipp Tomsich, Caroline Trippel, Ray VanDeWalker, Muralidaran Vijayaraghavan, Megan Wachs, Andrew Waterman, Robert Watson, David Weaver, Derek Williams, Andrew Wright, Reinoud Zandijk,
 and Sizhuo Zhang._
 
 _This document is released under a Creative Commons Attribution 4.0 International License._
@@ -126,6 +121,7 @@ include::zfa.adoc[]
 //zfa.tex
 include::ztso-st-ext.adoc[]
 //ztso.tex
+include::zawrs.adoc[]
 
 include::zc/Zc.adoc[]
 
diff --git a/src/rv-32-64g.adoc b/src/rv-32-64g.adoc
index 7714436..1818ddf 100644
--- a/src/rv-32-64g.adoc
+++ b/src/rv-32-64g.adoc
@@ -442,6 +442,15 @@ ISA.
 2+|1101010 |00011 |rs1 |rm |rd |1010011 |FCVT.H.LU
 |===
 
+[%autowidth.stretch,float="center",align="center",cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"]
+|===
+15+^|Zawrs Standard Extension
+
+6+^|000000001101 2+^|00000 2+^|000 2+^|00000 2+^|1110011 <|WRS.NTO
+6+^|000000011101 2+^|00000 2+^|000 2+^|00000 2+^|1110011 <|WRS.STO
+|===
+
+
 <<rvgcsrnames>> lists the CSRs that have currently been
 allocated CSR addresses. The timers, counters, and floating-point CSRs
 are the only CSRs defined in this specification.
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index 85f0ec2..2b30893 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -1,5 +1,5 @@
 [[supervisor]]
-== Supervisor-Level ISA, Version 1.12
+== Supervisor-Level ISA, Version 1.13
 
 This chapter describes the RISC-V supervisor-level architecture, which
 contains a common core that is used with various supervisor-level
@@ -287,6 +287,15 @@ interrupt-enable bits for supervisor-level software interrupts. If
 implemented, SSIP is writable in `sip` and may also be set to 1 by a
 platform-specific interrupt controller.
 
+If the Sscofpmf extension is implemented, bits `sip`.LCOFIP and `sie`.LCOFIE
+are the interrupt-pending and interrupt-enable bits for local counter-overflow
+interrupts.
+LCOFIP is read-write in `sip` and reflects the occurrence of a local
+counter-overflow overflow interrupt request resulting from any of the
+`mhpmevent__n__`.OF bits being set.
+If the Sscofpmf extension is not implemented, `sip`.LCOFIP and `sie`.LCOFIE are
+read-only zeros.
+
 [NOTE]
 ====
 Interprocessor interrupts are sent to other harts by
@@ -294,7 +303,7 @@ implementation-specific means, which will ultimately cause the SSIP bit
 to be set in the recipient hart’s `sip` register.
 ====
 
-Each standard interrupt type (SEI, STI, or SSI) may not be implemented,
+Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented,
 in which case the corresponding interrupt-pending and interrupt-enable
 bits are read-only zeros. All bits in `sip` and `sie` are *WARL* fields. The
 implemented interrupts may be found by writing one to every bit location
@@ -315,7 +324,7 @@ M-mode to S-mode, they are shown as 0 in
 ====
 
 Multiple simultaneous interrupts destined for supervisor mode are
-handled in the following decreasing priority order: SEI, SSI, STI.
+handled in the following decreasing priority order: SEI, SSI, STI, LCOFI.
 
 ==== Supervisor Timers and Performance Counters
 
@@ -445,7 +454,7 @@ Supervisor timer interrupt +
 _Reserved_ +
 Supervisor external interrupt +
 _Reserved_ +
-_Reserved for counter-overflow interrupt_ +
+Counter-overflow interrupt +
 _Reserved_ +
 _Designated for platform use_ 
 
@@ -1837,7 +1846,7 @@ associated memory pages. The encoding for the PBMT bits is captured in
 The Svpbmt extension depends on Sv39.
 
 [[pbmt]]
-.Encodings for PBMT field in Sv39, Sv48, and Sv57 PTEs.  Attributes not mentioned are inherited from PMA associated with the physical address.
+.Encodings for PBMT field in Sv39, Sv48, and Sv57 PTEs.
 [%autowidth,float="center",align="center",cols="^,^,<",options="header"]
 |===
 |Mode |Value |Requested Memory Attributes
@@ -1855,6 +1864,13 @@ Non-cacheable, non-idempotent, strongly-ordered (I/O ordering), I/O +
 _Reserved for future standard use_
 |===
 
+Implementations may override additional PMAs not explicitly listed in
+<<pbmt>>.
+For example, to be consistent with the characteristics of a typical I/O region,
+a misaligned memory access to a page with PBMT=IO might raise an exception,
+even if the underlying region were main memory and the same access would have
+succeeded for PBMT=PMA.
+
 [NOTE]
 ====
 Future extensions may provide more and/or finer-grained control over
diff --git a/src/zawrs.adoc b/src/zawrs.adoc
new file mode 100644
index 0000000..456c582
--- /dev/null
+++ b/src/zawrs.adoc
@@ -0,0 +1,105 @@
+== "Zawrs" Statndard extension for Wait-on-Reservation-Set instructions, Version 1.01
+
+The Zawrs extension defines a pair of instructions to be used in polling loops 
+that allows a core to enter a low-power state and wait on a store to a memory 
+location. Waiting for a memory location to be updated is a common pattern in 
+many use cases such as:
+
+. Contenders for a lock waiting for the lock variable to be updated.
+
+. Consumers waiting on the tail of an empty queue for the producer to queue 
+  work/data. The producer may be code executing on a RISC-V hart, an accelerator
+  device, an external I/O agent.
+
+. Code waiting on a flag to be set in memory indicative of an event occurring. 
+  For example, software on a RISC-V hart may wait on a "done" flag to be set in
+  memory by an accelerator device indicating completion of a job previously 
+  submitted to the device.
+
+Such use cases involve polling on memory locations, and such busy loops can be a
+wasteful expenditure of energy. To mitigate the wasteful looping in such usages,
+a `WRS.NTO` (WRS-with-no-timeout) instruction is provided. Instead of polling 
+for a store to a specific memory location, software registers a reservation set
+that includes all the bytes of the memory location using the `LR` instruction. 
+Then a subsequent `WRS.NTO` instruction would cause the hart to temporarily 
+stall execution in a low-power state until a store occurs to the reservation set
+or an interrupt is observed.
+
+Sometimes the program waiting on a memory update may also need to carry out a
+task at a future time or otherwise place an upper bound on the wait. To support
+such use cases a second instruction `WRS.STO` (WRS-with-short-timeout) is 
+provided that works like `WRS.NTO` but bounds the stall duration to an 
+implementation-define short timeout such that the stall is terminated on the 
+timeout if no other conditions have occurred to terminate the stall. The 
+program using this instruction may then determine if its deadline has been 
+reached.
+
+[NOTE]
+====
+The instructions in the Zawrs extension are only useful in conjunction with the
+LR instruction, which is provided by the A extension, and which we also expect
+to be provided by a narrower Zalrsc extension in the future.
+====
+[[Zawrs]]
+=== Wait-on-Reservation-Set Instructions
+
+The `WRS.NTO` and `WRS.STO` instructions cause the hart to temporarily stall
+execution in a low-power state as long as the reservation set is valid and no
+pending interrupts, even if disabled, are observed. For `WRS.STO` the stall 
+duration is bounded by an implementation defined short timeout. These 
+instructions are available in all privilege modes. These instructions are not
+supported in a constrained `LR`/`SC` loop.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['SYSTEM(0x73)'] },
+  {bits: 5, name: 'rd', attr: ['0'] },
+  {bits: 3,  name: 'funct3', attr: ['0'] },
+  {bits: 5,  name: 'rs1', attr: ['0'] },
+  {bits: 12,  name: 'funct12', attr:['WRS.NTO(0x0d)', 'WRS.STO(0x1d)'] },
+], config:{lanes: 1, hspace:1024}}
+....
+
+<<<
+
+Hart execution may be stalled while the following conditions are all satisfied:
+[loweralpha]
+    . The reservation set is valid 
+    . If `WRS.STO`, a "short" duration since start of stall has not elapsed
+    . No pending interrupt is observed (see the rules below)
+
+While stalled, an implementation is permitted to occasionally terminate the 
+stall and complete execution for any reason. 
+
+`WRS.NTO` and `WRS.STO` instructions follow the rules of the `WFI` instruction
+for resuming execution on a pending  interrupt.
+
+When the `TW` (Timeout Wait) bit in `mstatus` is set and `WRS.NTO` is executed
+in any privilege mode other than M mode, and it does not complete within an
+implementation-specific bounded time limit, the `WRS.NTO` instruction will cause
+an illegal instruction exception.
+
+When executing in VS or VU mode, if the `VTW` bit is set in `hstatus`, the 
+`TW` bit in `mstatus` is clear, and the `WRS.NTO` does not complete within an 
+implementation-specific bounded time limit, the `WRS.NTO` instruction will cause
+a virtual instruction exception.
+
+[NOTE]
+====
+Since the `WRS.STO` and `WRS.NTO` instructions can complete execution for 
+reasons other than stores to the reservation set, software will likely need 
+a means of looping until the required stores have occurred.
+
+The duration of a `WRS.STO` instruction's timeout may vary significantly within 
+and among implementations. In typical implementations this duration should be 
+roughly in the range of 10 to 100 times an on-chip cache miss latency or a 
+cacheless access to main memory.
+
+`WRS.NTO`, unlike `WFI`, is not specified to cause an illegal instruction
+exception if executed in U-mode when the governing `TW` bit is 0. `WFI` is
+typically not expected to be used in U-mode and on many systems may promptly
+cause an illegal instruction exception if used at U-mode. Unlike `WFI`,
+`WRS.NTO` is expected to be used by software in U-mode when waiting on
+memory but without a deadline for that wait.
+====
\ No newline at end of file