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author | Andrew Waterman <andrew@sifive.com> | 2018-05-25 18:32:24 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-05-25 18:32:24 -0700 |
commit | 4a29140ef57e38532b3d3e43c9cd49e07066e7e0 (patch) | |
tree | 310c2d107f395b969e26e65bf41da5f99e49d191 | |
parent | 62a674e5f123df5369410e09544c71ffa1566cdd (diff) | |
download | riscv-isa-manual-4a29140ef57e38532b3d3e43c9cd49e07066e7e0.zip riscv-isa-manual-4a29140ef57e38532b3d3e43c9cd49e07066e7e0.tar.gz riscv-isa-manual-4a29140ef57e38532b3d3e43c9cd49e07066e7e0.tar.bz2 |
PMP changes need an SFENCE when VM is enabled
-rw-r--r-- | src/machine.tex | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index ecfd5ba..3185598 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2905,3 +2905,28 @@ that passes the PMP check may become visible, even if another portion fails the PMP check. The same behavior may manifest for floating-point stores wider than XLEN bits (e.g., the FSD instruction in RV32D), even when the store address is naturally aligned. + +\subsection{Physical Memory Protection and Paging} + +The Physical Memory Protection mechanism is designed to compose with the +page-based virtual memory systems described in Chapter~\ref{supervisor}. When +paging is enabled, instructions that access virtual memory may result in +multiple physical-memory accesses, including implicit references to the page +tables. The PMP checks apply to all of these accesses. The effective +privilege mode for implicit page-table accesses is S. + +Implementations with virtual memory are permitted to perform address +translations speculatively and earlier than required by an explicit +virtual-memory access. The PMP settings for the resulting physical address +may be checked at any point between the address translation and the explicit +virtual-memory access. Hence, when the PMP settings are modified in a manner +that affects either the physical memory that holds the page tables or the +physical memory to which the page tables point, M-mode software must +synchronize the PMP settings with the virtual memory system. This is +accomplished by executing an SFENCE.VMA instruction with {\em rs1}={\tt x0} +and {\em rs2}={\tt x0}, after the PMP CSRs are written. Note, SFENCE.VMA is +only guaranteed to synchronize the PMP settings with the virtual memory system +when it is executed in M-mode. + +If page-based virtual memory is not implemented, or when it is disabled, +memory accesses check the PMP settings synchronously, so no fence is needed. |