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| author | Andrew Waterman <andrew@sifive.com> | 2024-07-24 18:43:00 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-25 01:43:00 +0000 |
| commit | 456e2f9bd8114b2d5fd3031ea5ebb4a965186435 (patch) | |
| tree | f32467056efdb340288c0048b9af9f1df2f51a16 | |
| parent | 9f10757fab31ca82ad16f128c14549508e2baf24 (diff) | |
| download | riscv-isa-manual-456e2f9bd8114b2d5fd3031ea5ebb4a965186435.zip riscv-isa-manual-456e2f9bd8114b2d5fd3031ea5ebb4a965186435.tar.gz riscv-isa-manual-456e2f9bd8114b2d5fd3031ea5ebb4a965186435.tar.bz2 | |
Add tag to senvcfg section (#1562)riscv-isa-release-456e2f9-2024-07-25
| -rw-r--r-- | src/supervisor.adoc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc index d6d52b1..fee952f 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -711,6 +711,7 @@ instruction bits is implemented, `stval` must also be able to hold all values less than latexmath:[$2^N$], where latexmath:[$N$] is the smaller of SXLEN and ILEN. +[[sec:senvcfg]] ==== Supervisor Environment Configuration (`senvcfg`) Register The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as |