diff options
| author | Andrew Waterman <andrew@sifive.com> | 2018-11-06 19:40:05 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-06 19:40:05 -0800 |
| commit | 399c74ab450e9ce34944a1a8e06de93b250efd84 (patch) | |
| tree | 62564dddb26061262e0ad17cca3e05b495edb5f4 | |
| parent | e2c243a3b1056fbd8b34b8b222a0467f405c0e21 (diff) | |
| download | riscv-isa-manual-399c74ab450e9ce34944a1a8e06de93b250efd84.zip riscv-isa-manual-399c74ab450e9ce34944a1a8e06de93b250efd84.tar.gz riscv-isa-manual-399c74ab450e9ce34944a1a8e06de93b250efd84.tar.bz2 | |
spelling20181106-Base-Ratification
| -rw-r--r-- | src/machine.tex | 2 | ||||
| -rw-r--r-- | src/preface.tex | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index 0341cc7..6de2495 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1396,7 +1396,7 @@ Synchronous exceptions are of lower priority than all interrupts. with the following rationale. Interrupts for higher privilege modes must be serviced before - interrupts for lower privilege modes to support pre-emption. + interrupts for lower privilege modes to support preemption. The platform-specific machine-level interrupt sources in bits 16 and above have platform-specific priority, but are typically chosen to have the diff --git a/src/preface.tex b/src/preface.tex index 0410047..55499cd 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -59,7 +59,7 @@ The changes in this version of the document include: \item Changed document version scheme to avoid confusion with versions of the ISA modules. \item Incremented the version numbers of the base integer ISA to 2.1, - reflecting the prescence of the ratified RVWMO memory model and + reflecting the presence of the ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA. \item Incremented the version numbers of the F and D extensions to 2.2, |