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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-15 23:28:53 -0500 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-15 23:28:53 -0500 |
| commit | 2d12caabaf2bed535adbd0607efab59114d89947 (patch) | |
| tree | 5889c49544c6f11a06a9fe7dd75b5ce541a63f22 | |
| parent | 9d6188bd9659b0d28f05d2924458e99e0f609895 (diff) | |
| download | riscv-isa-manual-2d12caabaf2bed535adbd0607efab59114d89947.zip riscv-isa-manual-2d12caabaf2bed535adbd0607efab59114d89947.tar.gz riscv-isa-manual-2d12caabaf2bed535adbd0607efab59114d89947.tar.bz2 | |
Move ILEN definition to introduction
| -rw-r--r-- | src/extensions.tex | 9 | ||||
| -rw-r--r-- | src/intro.tex | 9 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/extensions.tex b/src/extensions.tex index efd0760..4346422 100644 --- a/src/extensions.tex +++ b/src/extensions.tex @@ -52,15 +52,6 @@ example, the base ISA is defined within a 30-bit encoding space (bits 31--2 of the 32-bit instruction), while the atomic extension ``A'' fits within a 25-bit encoding space (bits 31--7). -We use the term ILEN to refer to the maximum instruction length supported -by an implementation, which is always a multiple of 16 bits. For -implementations supporting only the base instruction set, ILEN is 32 bits. -Implementations supporting longer instructions have larger values of ILEN. -ILEN is implied from the set of extensions implemented, or can be -explicitly defined in the platform configuration if an implementation is -designed to support an extension that uses longer instructions via software -emulation but does not actually decode longer instructions in hardware. - We use the term {\em prefix} to refer to the bits to the {\em right} of an instruction encoding space (since RISC-V is little-endian, the bits to the right are stored at earlier memory addresses, hence form a diff --git a/src/intro.tex b/src/intro.tex index 1ff8139..c531a2c 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -323,6 +323,15 @@ providing compressed 16-bit instructions and relaxes the alignment constraints to allow all instructions (16 bit and 32 bit) to be aligned on any 16-bit boundary to improve code density. +We use the term ILEN to refer to the maximum instruction length supported +by an implementation, which is always a multiple of 16 bits. For +implementations supporting only the base instruction set, ILEN is 32 bits. +Implementations supporting longer instructions have larger values of ILEN. +ILEN is implied from the set of extensions implemented, or can be +explicitly defined in the platform configuration if an implementation is +designed to support an extension that uses longer instructions via software +emulation but does not actually decode longer instructions in hardware. + Figure~\ref{instlengthcode} illustrates the standard RISC-V instruction-length encoding convention. All the 32-bit instructions in the base ISA have their lowest two bits set to {\tt 11}. The |